NXP T2080 Port Refresh

Author: dgarske

arch.mk

@@ -633,6 +633,13 @@ ifeq ($(ARCH),PPC)
     CFLAGS+=-fno-builtin-printf
   endif
 
+  # Target-specific CPU flags
+  ifeq ($(TARGET),nxp_t2080)
+    CFLAGS+=-mcpu=e6500 -mno-altivec
+  else ifeq ($(TARGET),nxp_t1024)
+    CFLAGS+=-mcpu=e5500
+  endif
+
   # Prune unused functions and data
   CFLAGS+=-ffunction-sections -fdata-sections
   LDFLAGS+=-Wl,--gc-sections

hal/nxp_ppc.h

@@ -101,7 +101,7 @@
     #define USE_LONG_JUMP
 
 #elif defined(TARGET_nxp_t2080)
-    /* NXP T0280 */
+    /* NXP T2080 */
     #define CORE_E6500
     #define CPU_NUMCORES 4
     #define CORES_PER_CLUSTER 4
@@ -118,13 +118,16 @@
     #define ENABLE_L1_CACHE
     #define ENABLE_L2_CACHE
 
-    #define L2SRAM_ADDR   (0xF8F80000UL) /* L2 as SRAM */
-    #define L2SRAM_SIZE   (256UL * 1024UL)
+    #define L2SRAM_ADDR   (0xF8F00000UL) /* CPC as SRAM (1MB) */
+    #define L2SRAM_SIZE   (1024UL * 1024UL)
 
     #define INITIAL_SRAM_ADDR     L2SRAM_ADDR
-    #define INITIAL_SRAM_LAW_SZ   LAW_SIZE_256KB
+    /* CPC SRAM transactions traverse the CoreNet interconnect, which
+     * requires a LAW to route them. LAW_TRGT_DDR_1 is used as a routing
+     * target; the CPC intercepts the transaction before it reaches DDR. */
+    #define INITIAL_SRAM_LAW_SZ   LAW_SIZE_1MB
     #define INITIAL_SRAM_LAW_TRGT LAW_TRGT_DDR_1
-    #define INITIAL_SRAM_BOOKE_SZ BOOKE_PAGESZ_256K
+    #define INITIAL_SRAM_BOOKE_SZ BOOKE_PAGESZ_1M
 
     #define ENABLE_INTERRUPTS
 
@@ -285,20 +288,23 @@
     #define CPC_BASE            (CCSRBAR + 0x10000)
     /* 8.2 CoreNet Platform Cache (CPC) Memory Map */
     #define CPCCSR0             (0x000)
+    #define CPCEWCR0            (0x010)
     #define CPCSRCR1            (0x100)
     #define CPCSRCR0            (0x104)
+    #define CPCERRDIS           (0xE44)
     #define CPCHDBCR0           (0xF00)
 
     #define CPCCSR0_CPCE        (0x80000000 >> 0)
     #define CPCCSR0_CPCPE       (0x80000000 >> 1)
     #define CPCCSR0_CPCFI       (0x80000000 >> 10)
+    #define CPCCSR0_CPCFL       (0x80000000 >> 20)
     #define CPCCSR0_CPCLFC      (0x80000000 >> 21)
-    #define CPCCSR0_SRAM_ENABLE (CPCCSR0_CPCE | CPCCSR0_CPCPE)
 
     #ifdef CORE_E6500
-        #define CPCSRCR0_SRAMSZ_64  (0x1 << 1) /* ways 14-15 */
-        #define CPCSRCR0_SRAMSZ_256 (0x3 << 1) /* ways 8-15 */
-        #define CPCSRCR0_SRAMSZ_512 (0x4 << 1) /* ways 0-15 */
+        /* T2080: 2MB CPC, 16 ways, 128KB per way */
+        #define CPCSRCR0_SRAMSZ_256  (0x1 << 1) /* ways 14-15, 256KB */
+        #define CPCSRCR0_SRAMSZ_1024 (0x3 << 1) /* ways 8-15, 1MB */
+        #define CPCSRCR0_SRAMSZ_2048 (0x4 << 1) /* ways 0-15, 2MB */
     #else /* CORE E5500 */
         #define CPCSRCR0_SRAMSZ_64  (0x1 << 1) /* ways 6-7 */
         #define CPCSRCR0_SRAMSZ_128 (0x2 << 1) /* ways 4-7 */
@@ -483,13 +489,21 @@
 
 #define SPRN_DBSR 0x130 /* Debug Status Register */
 #define SPRN_DEC  0x016 /* Decrement Register */
-#define SPRN_TSR  0x3D8 /* Timer Status Register */
 
-#define SPRN_TCR  0x3DA /* Timer Control Register */
+#ifdef CORE_E6500
+    #define SPRN_TSR  0x150 /* Timer Status Register (SPR 336) */
+    #define SPRN_TCR  0x154 /* Timer Control Register (SPR 340) */
+    #define SPRN_DEAR 0x03D /* Data Exception Address Register (SPR 61) */
+    #define SPRN_ESR  0x03E /* Exception Syndrome Register (SPR 62) */
+#else
+    #define SPRN_TSR  0x3D8 /* Timer Status Register */
+    #define SPRN_TCR  0x3DA /* Timer Control Register */
+    #define SPRN_DEAR 0x3D5 /* Data Exception Address Register */
+    #define SPRN_ESR  0x3D4 /* Exception Syndrome Register */
+#endif
+
 #define TCR_WIE   0x08000000 /* Watchdog Interrupt Enable */
 #define TCR_DIE   0x04000000 /* Decrement Interrupt Enable */
-
-#define SPRN_ESR  0x3D4 /* Exception Syndrome Register */
 #define SPRN_MCSR 0x23C /* Machine Check Syndrome Register */
 #define SPRN_PVR  0x11F /* Processor Version */
 #define SPRN_SVR  0x3FF /* System Version */
@@ -524,6 +538,8 @@
 
 #define SRR0     0x01A   /* Save/Restore Register 0 */
 #define SRR1     0x01B   /* Save/Restore Register 1 */
+#define SPRN_MCSRR0  0x23A /* Machine Check Save/Restore Register 0 */
+#define SPRN_MCSRR1  0x23B /* Machine Check Save/Restore Register 1 */
 
 #define MSR_DS   (1<<4)  /* Book E Data address space */
 #define MSR_IS   (1<<5)  /* Book E Instruction address space */
@@ -674,6 +690,31 @@ extern void dcache_disable(void);
 
 #else
 /* Assembly version */
+#ifdef CORE_E6500
+/* e6500 has 64-bit MAS registers - must clear upper 32 bits */
+#define set_tlb(tlb, esel, epn, rpn, urpn, perms, winge, ts, tsize, iprot, reg) \
+    lis   reg, BOOKE_MAS0(tlb, esel, 0)@h; \
+    ori   reg, reg, BOOKE_MAS0(tlb, esel, 0)@l; \
+    mtspr MAS0, reg;\
+    lis   reg, BOOKE_MAS1(1, iprot, 0, ts, tsize)@h; \
+    ori   reg, reg, BOOKE_MAS1(1, iprot, 0, ts, tsize)@l; \
+    mtspr MAS1, reg; \
+    li    reg, 0; \
+    oris  reg, reg, BOOKE_MAS2(epn, winge)@h; \
+    ori   reg, reg, BOOKE_MAS2(epn, winge)@l; \
+    mtspr MAS2, reg; \
+    lis   reg, BOOKE_MAS3(rpn, 0, perms)@h; \
+    ori   reg, reg, BOOKE_MAS3(rpn, 0, perms)@l; \
+    mtspr MAS3, reg; \
+    lis   reg, urpn@h; \
+    ori   reg, reg, urpn@l; \
+    mtspr MAS7, reg; \
+    isync; \
+    msync; \
+    tlbwe; \
+    isync;
+#else
+/* e500/e5500 - 32-bit MAS registers */
 #define set_tlb(tlb, esel, epn, rpn, urpn, perms, winge, ts, tsize, iprot, reg) \
     lis   reg, BOOKE_MAS0(tlb, esel, 0)@h; \
     ori   reg, reg, BOOKE_MAS0(tlb, esel, 0)@l; \
@@ -694,6 +735,7 @@ extern void dcache_disable(void);
     msync; \
     tlbwe; \
     isync;
+#endif /* CORE_E6500 */
 
     /* readability helpers for assembly to show register versus decimal */
     #define r0 0