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dgarskedgarske
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Add wolfBoot port for STM32N6 (NUCLEO-N657X0-Q)
Co-authored-by: Aidan Garske <aidan@wolfssl.com>
1 parent c3d255d commit 8351b49

18 files changed

Lines changed: 2496 additions & 11 deletions

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‎.github/workflows/test-configs.yml‎

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@@ -456,6 +456,18 @@ jobs:
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arch: arm
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config-file: ./config/examples/stm32h5-dualbank.config
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stm32n6_test:
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uses: ./.github/workflows/test-build.yml
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with:
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arch: arm
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config-file: ./config/examples/stm32n6.config
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stm32n6_tz_test:
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uses: ./.github/workflows/test-build.yml
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with:
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arch: arm
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config-file: ./config/examples/stm32n6-tz.config
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stm32h5_tz_test:
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uses: ./.github/workflows/test-build.yml
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with:

‎Makefile‎

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@@ -242,6 +242,11 @@ ifeq ($(TARGET),stm32h5)
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# Don't build a contiguous image
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MAIN_TARGET:=wolfboot.bin test-app/image_v1_signed.bin
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endif
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ifeq ($(TARGET),stm32n6)
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# Don't build a contiguous image
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MAIN_TARGET:=wolfboot.bin test-app/image_v1_signed.bin
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endif
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endif # TZEN=1
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ifeq ($(TARGET),x86_64_efi)
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MAIN_TARGET:=wolfboot.bin test-app/image_v1_signed.bin
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endif
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ifeq ($(TARGET),stm32n6)
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# wolfBoot runs from SRAM, app from XIP on external NOR - no contiguous factory.bin
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MAIN_TARGET:=wolfboot.bin test-app/image_v1_signed.bin
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endif
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ifeq ($(TARGET),rp2350)
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MAIN_TARGET:=include/target.h keytools wolfboot_signing_private_key.der pico-sdk-info
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endif
@@ -684,6 +694,12 @@ stack-usage: wolfboot.bin
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image-header-size: wolfboot.bin
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$(Q)echo $(IMAGE_HEADER_SIZE) > .image_header_size
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## Target-specific flash targets
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ifeq ($(TARGET),stm32n6)
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flash: wolfboot.bin test-app/image_v1_signed.bin
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$(Q)tools/scripts/stm32n6_flash.sh --skip-build
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endif
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cppcheck:
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cppcheck -f --enable=warning --enable=portability \

‎arch.mk‎

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@@ -290,6 +290,18 @@ ifeq ($(ARCH),ARM)
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endif
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ifeq ($(TARGET),stm32n6)
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CORTEX_M55=1
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CFLAGS+=-Ihal
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ARCH_FLASH_OFFSET=0x70000000
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# Boot ROM copies FSBL from NOR to AXISRAM2 at 0x34180400.
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# The signing -la flag in the flash script must match.
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WOLFBOOT_ORIGIN=0x34180400
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EXT_FLASH=1
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PART_UPDATE_EXT=1
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PART_SWAP_EXT=1
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endif
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ifeq ($(TARGET),rp2350)
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CORTEX_M33=1
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CFLAGS+=-Ihal
@@ -442,12 +454,22 @@ else
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CORTEXM_ARM_EXTRA_CFLAGS+=-DWOLFSSL_ARMASM -DWOLFSSL_ARMASM_NO_HW_CRYPTO \
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-DWOLFSSL_ARMASM_NO_NEON -DWOLFSSL_ARMASM_THUMB2
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endif
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ifeq ($(CORTEX_M55),1)
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CORTEX_M33=1
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CFLAGS+=-mcpu=cortex-m55 -DCORTEX_M55
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LDFLAGS+=-mcpu=cortex-m55
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endif
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ifeq ($(CORTEX_M33),1)
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CFLAGS+=-mcpu=cortex-m33 -DCORTEX_M33
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LDFLAGS+=-mcpu=cortex-m33
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CFLAGS+=-DCORTEX_M33
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ifneq ($(CORTEX_M55),1)
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CFLAGS+=-mcpu=cortex-m33
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LDFLAGS+=-mcpu=cortex-m33
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endif
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ifeq ($(TZEN),1)
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ifneq (,$(findstring stm32,$(TARGET)))
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OBJS+=hal/stm32_tz.o
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ifneq ($(TARGET),stm32n6)
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OBJS+=hal/stm32_tz.o
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endif
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endif
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CFLAGS+=-mcmse
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SECURE_LDFLAGS+=-Wl,--cmse-implib -Wl,--out-implib=./src/wolfboot_tz_nsc.o

‎config/examples/stm32n6-tz.config‎

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ARCH?=ARM
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TARGET?=stm32n6
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TZEN?=1
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SIGN?=ECC256
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HASH?=SHA256
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DEBUG?=0
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DEBUG_UART?=1
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VTOR?=1
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NO_ASM?=0
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NO_MPU=1
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SPI_FLASH?=0
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ALLOW_DOWNGRADE?=0
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NVM_FLASH_WRITEONCE?=0
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WOLFBOOT_VERSION?=1
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V?=0
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SPMATH?=1
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RAM_CODE?=1
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WOLFBOOT_SECTOR_SIZE?=0x1000
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WOLFBOOT_PARTITION_SIZE?=0x100000
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# Boot partition: secure alias (0x70180000). N6 IDAU appears hard-
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# wired Secure for the low 1 MB of XSPI2 (0x70000000..0x700FFFFF) and
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# deferring to SAU above 0x70100000 -- ST's Template_Isolation_XIP
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# reference puts its NS app at 0x70180000 for this reason. SAU REG[2]
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# classifies the boot partition window NS so the secure CPU's reads
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# (during verify) and the NS CPU's XIP fetches (post-BLXNS) both
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# succeed through the same address.
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WOLFBOOT_PARTITION_BOOT_ADDRESS?=0x70180000
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WOLFBOOT_PARTITION_UPDATE_ADDRESS?=0x00280000
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WOLFBOOT_PARTITION_SWAP_ADDRESS?=0x00170000
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IMAGE_HEADER_SIZE?=1024
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# Boot partition is on the same XSPI2 NOR flash as update/swap.
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# PART_BOOT_EXT routes boot partition reads through ext_flash API (SPI
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# commands) instead of XIP, avoiding bus faults when XSPI2 toggles
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# between memory-mapped and command mode during firmware updates.
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CFLAGS_EXTRA+=-DPART_BOOT_EXT
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BOOTLOADER_PARTITION_SIZE=0x40000
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# NSC veneers: placed in the NS alias of the top 4 KB of wolfBoot's
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# 256 KB AXISRAM2 region. Physical bytes are shared with FLASH (same
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# SRAM); SAU promotes this NS view to NSC so secure-gateway stubs are
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# reachable via BLXNS from the NS app. WOLFCRYPT_TZ is off in this
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# config, so the section is empty -- but the linker requires a home.
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WOLFBOOT_NSC_ADDRESS?=0x2418F000
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WOLFBOOT_NSC_SIZE?=0x1000
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# Keyvault unused while WOLFCRYPT_TZ=0; reserve a small dummy region
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# so the H5-derived linker template substitutes cleanly.
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WOLFBOOT_KEYVAULT_ADDRESS?=0x2418E000
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WOLFBOOT_KEYVAULT_SIZE?=0x1000

‎config/examples/stm32n6.config‎

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ARCH?=ARM
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TARGET?=stm32n6
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SIGN?=ECC256
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HASH?=SHA256
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DEBUG?=0
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DEBUG_UART?=1
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VTOR?=1
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NO_ASM?=0
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NO_MPU=1
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SPI_FLASH?=0
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ALLOW_DOWNGRADE?=0
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NVM_FLASH_WRITEONCE?=0
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WOLFBOOT_VERSION?=1
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V?=0
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SPMATH?=1
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RAM_CODE?=1
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WOLFBOOT_SECTOR_SIZE?=0x1000
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WOLFBOOT_PARTITION_SIZE?=0x100000
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WOLFBOOT_PARTITION_BOOT_ADDRESS?=0x70020000
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WOLFBOOT_PARTITION_UPDATE_ADDRESS?=0x00120000
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WOLFBOOT_PARTITION_SWAP_ADDRESS?=0x00010000
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IMAGE_HEADER_SIZE?=1024
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# Boot partition is on the same XSPI2 NOR flash as update/swap.
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# PART_BOOT_EXT ensures boot partition reads go through ext_flash API
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# (SPI commands) instead of XIP, avoiding bus faults when XSPI2 toggles
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# between memory-mapped and command mode during firmware updates.
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CFLAGS_EXTRA+=-DPART_BOOT_EXT
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# Enable verbose fault handler so a hardfault prints registers via UART
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CFLAGS_EXTRA+=-DDEBUG_HARDFAULT
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BOOTLOADER_PARTITION_SIZE=0x40000

‎config/openocd/openocd_stm32n6.cfg‎

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# OpenOCD config for NUCLEO-N657X0-Q with MX25UM51245G NOR on XSPI2
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source [find interface/stlink.cfg]
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transport select swd
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set CHIPNAME stm32n6x
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set WORKAREASIZE 0x10000
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source [find target/stm32n6x.cfg]
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# Work-area above wolfBoot SRAM region
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$_TARGETNAME configure -work-area-phys 0x34020000 -work-area-size $WORKAREASIZE -work-area-backup 0
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# XSPI2 NOR flash bank (memory-mapped at 0x70000000, regs at 0x5802A000)
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set XSPI2_BANK_ID [llength [flash list]]
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flash bank $CHIPNAME.xspi2 stmqspi 0x70000000 0 0 0 $CHIPNAME.cpu 0x5802A000
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# Mark VDDIO supplies valid (required for XSPI2 GPIO)
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proc pwr_enable_io_supply {} {
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mmw 0x5602825C 0x00040000 0 ;# RCC_AHB4ENR: PWR clock
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mmw 0x56024834 0x00000100 0 ;# SVMCR1: VDDIO4SV
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mmw 0x56024838 0x00000100 0 ;# SVMCR2: VDDIO5SV
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mmw 0x5602483C 0x00000300 0 ;# SVMCR3: VDDIO2SV + VDDIO3SV
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}
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# Port N GPIO for XSPI2 (PN0-PN11, AF9, very high speed)
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proc xspi2_gpio_init {} {
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mmw 0x5602825C 0x00002000 0 ;# RCC_AHB4ENR: GPION clock
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sleep 1
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mmw 0x56023400 0x00AAAAAA 0x00555555 ;# MODER: AF mode
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mmw 0x56023408 0x00FFFFFF 0 ;# OSPEEDR: very high
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mmw 0x5602340C 0 0x00FFFFFF ;# PUPDR: no pull
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mww 0x56023420 0x99999999 ;# AFRL: AF9
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mww 0x56023424 0x00009999 ;# AFRH: AF9
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}
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# XSPI2 init: single-SPI, /16 prescaler, NOR reset, enter mmap mode
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proc xspi2_init {} {
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mmw 0x56028260 0x00003000 0 ;# RCC_AHB5ENR: XSPI2 + XSPIM clocks
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mmw 0x56028248 0x00000008 0 ;# RCC_MISCENR: XSPI PHY comp clock
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sleep 1
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mww 0x5802A000 0x00000000 ;# CR: disable
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sleep 1
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mww 0x5802A008 0x001A0308 ;# DCR1: DLYBYP, DEVSIZE=26, CSHT=3
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mww 0x5802A00C 0x0000000F ;# DCR2: prescaler /16
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sleep 1
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mww 0x5802A000 0x00000001 ;# CR: enable
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# NOR flash software reset (0x66 + 0x99)
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mmw 0x5802A000 0x00000002 0 ;# abort
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sleep 1
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mww 0x5802A024 0x0000000B ;# FCR: clear flags
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mww 0x5802A100 0x00000001 ;# CCR: IMODE=single
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mww 0x5802A108 0x00000000 ;# TCR: no dummy
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mww 0x5802A110 0x00000066 ;# IR: Reset Enable
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sleep 1
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mmw 0x5802A000 0x00000002 0 ;# abort
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sleep 1
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mww 0x5802A024 0x0000000B
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mww 0x5802A100 0x00000001
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mww 0x5802A108 0x00000000
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mww 0x5802A110 0x00000099 ;# IR: Reset Memory
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sleep 10
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xspi2_mem_mapped
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}
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# Memory-mapped fast-read mode (single-SPI, 4-byte addr, 8 dummy cycles)
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proc xspi2_mem_mapped {} {
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mmw 0x5802A000 0x00000002 0 ;# abort
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sleep 1
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mww 0x5802A000 0x30000001 ;# CR: mmap + enable
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mww 0x5802A100 0x01003101 ;# CCR: IMODE=1, ADMODE=1, ADSIZE=3, DMODE=1
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mww 0x5802A108 0x40000008 ;# TCR: DCYC=8, SSHIFT
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mww 0x5802A110 0x0000000C ;# IR: Fast Read 4B
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}
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# Set NOR flash params manually (SFDP not readable in single-SPI mode)
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proc xspi2_flash_set {} {
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global XSPI2_BANK_ID
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stmqspi set $XSPI2_BANK_ID MX25UM51245G 0x4000000 0x100 0x13 0 0x12 0x60 0x1000 0x21
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}
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# Full reinit for use when XSPI2 may already be configured
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proc xspi2_reinit {} {
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global XSPI2_BANK_ID
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pwr_enable_io_supply
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xspi2_gpio_init
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xspi2_init
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xspi2_flash_set
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flash probe $XSPI2_BANK_ID
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xspi2_flash_set
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}
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$_TARGETNAME configure -event reset-init {
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global XSPI2_BANK_ID
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pwr_enable_io_supply
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xspi2_gpio_init
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xspi2_init
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xspi2_flash_set
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flash probe $XSPI2_BANK_ID
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# Re-set after probe (stmqspi driver quirk)
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xspi2_flash_set
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}
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init

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