Support for L2-LIM

Author: dgarske

Makefile

@@ -519,7 +519,8 @@ $(LSCRIPT): $(LSCRIPT_IN) FORCE
 		sed -e "s/@WOLFBOOT_LOAD_BASE@/$(WOLFBOOT_LOAD_BASE)/g" | \
 		sed -e "s/@BOOTLOADER_START@/$(BOOTLOADER_START)/g" | \
 		sed -e "s/@IMAGE_HEADER_SIZE@/$(IMAGE_HEADER_SIZE)/g" | \
-		sed -e "s/@FSP_S_LOAD_BASE@/$(FSP_S_LOAD_BASE)/g" \
+		sed -e "s/@FSP_S_LOAD_BASE@/$(FSP_S_LOAD_BASE)/g" | \
+		sed -e "s/@WOLFBOOT_L2LIM_SIZE@/$(WOLFBOOT_L2LIM_SIZE)/g" \
 		> $@
 
 hex: wolfboot.hex

arch.mk

@@ -596,8 +596,15 @@ ifeq ($(ARCH),RISCV64)
     # Use M-mode specific linker script
     LSCRIPT_IN:=hal/$(TARGET)-m.ld
   else
-    # Supervisor Mode (default): Running under HSS with DDR available
-    CFLAGS+=-DMMU -DWOLFBOOT_DUALBOOT
+    # Supervisor Mode: Running under HSS
+    CFLAGS+=-DWOLFBOOT_DUALBOOT
+    ifeq ($(MPFS_L2LIM),1)
+      # L2-LIM mode: wolfBoot in on-chip SRAM, loaded by HSS (no DDR)
+      LSCRIPT_IN:=hal/$(TARGET)-hss.ld
+    else
+      # DDR mode (default): full MMU and FDT support
+      CFLAGS+=-DMMU
+    endif
   endif
 
   # If SD card or eMMC is enabled use update_disk loader with GPT support
@@ -627,9 +634,11 @@ ifeq ($(ARCH),RISCV64)
     # U54 cores: rv64gc (with FPU)
     ARCH_FLAGS=-march=rv64imafd$(RISCV64_ZICSR)$(RISCV64_ZIFENCEI) -mabi=lp64d -mcmodel=medany
 
-    # FDT support required
-    CFLAGS+=-DWOLFBOOT_FDT
-    OBJS+=src/fdt.o
+    # FDT support for DDR S-mode (not needed for L2-LIM bare-metal boot)
+    ifneq ($(MPFS_L2LIM),1)
+      CFLAGS+=-DWOLFBOOT_FDT
+      OBJS+=src/fdt.o
+    endif
   endif
   CFLAGS+=-fno-builtin-printf -DUSE_M_TIME -g -nostartfiles -DARCH_RISCV -DARCH_RISCV64
   CFLAGS+=$(ARCH_FLAGS)

config/examples/polarfire_mpfs250_hss_l2lim.config

@@ -0,0 +1,93 @@
+ARCH?=RISCV64
+TARGET?=mpfs250
+
+# ECC P384 + SHA384
+SIGN?=ECC384
+HASH?=SHA384
+IMAGE_HEADER_SIZE=512
+
+WOLFBOOT_VERSION?=1
+ARMORED?=0
+DEBUG?=0
+DEBUG_SYMBOLS?=1
+DEBUG_UART?=1
+VTOR?=1
+
+NO_XIP?=1
+
+NVM_FLASH_WRITEONCE?=0
+UART_FLASH?=0
+V?=0
+NO_MPU?=1
+RAM_CODE?=0
+SPMATH?=1
+DUALBANK_SWAP?=0
+PKA?=0
+ENCRYPT=0
+WOLFTPM?=0
+ELF?=1
+#DEBUG_ELF?=1
+
+# Use RISC-V assembly version of ECDSA and SHA
+NO_ASM?=0
+
+# QSPI Flash Configuration
+# Using Micron MT25QL01GBBB (128MB, 64KB sectors)
+EXT_FLASH?=1
+SPI_FLASH?=0
+
+# SPI Flash Controller Selection:
+# MPFS_SC_SPI: Use SC QSPI Controller (0x37020100) for fabric-connected flash.
+#              Direct register access to System Controller's QSPI instance.
+# DEFAULT:     Use MSS QSPI Controller (0x21000000) for external flash
+#              on MSS QSPI pins.
+CFLAGS_EXTRA+=-DMPFS_SC_SPI
+
+# L2-LIM mode: wolfBoot loaded by HSS to L2-LIM (no DDR)
+# HSS runs on E51 from eNVM, loads wolfBoot to L2-LIM on U54 (S-mode)
+# wolfBoot loads application from SC ext SPI flash to L2-LIM
+MPFS_L2LIM?=1
+
+# wolfBoot origin in L2-LIM (above HSS resident region)
+# NOTE: Adjust based on HSS L2-LIM footprint. HSS typically uses ~200-400KB
+# from 0x08000000. Check HSS linker map for actual end address.
+WOLFBOOT_ORIGIN?=0x08040000
+
+# Application loaded from QSPI to L2-LIM (above wolfBoot, 128KB offset)
+WOLFBOOT_LOAD_ADDRESS?=0x08060000
+
+# Stack at top of 1.5MB L2-LIM (grows downward)
+WOLFBOOT_STACK_TOP?=0x08180000
+
+# L2-LIM size available for wolfBoot (STACK_TOP - ORIGIN)
+WOLFBOOT_L2LIM_SIZE?=0x140000
+
+# Flash geometry (64 KB sector)
+WOLFBOOT_SECTOR_SIZE?=0x10000
+
+# Partition layout for 128MB QSPI flash
+# Boot partition:     0x00020000 - 0x01FFFFFF (~32MB)
+# Update partition:   0x02000000 - 0x03FFFFFF (~32MB)
+# Swap partition:     0x04000000 - 0x0400FFFF (64KB)
+# Remaining:          0x04010000 - 0x07FFFFFF (~64MB available)
+WOLFBOOT_PARTITION_SIZE?=0x1FE0000
+WOLFBOOT_PARTITION_BOOT_ADDRESS?=0x20000
+WOLFBOOT_PARTITION_UPDATE_ADDRESS?=0x2000000
+WOLFBOOT_PARTITION_SWAP_ADDRESS?=0x4000000
+
+# Speed up reads from flash by using larger blocks
+CFLAGS_EXTRA+=-DWOLFBOOT_SHA_BLOCK_SIZE=4096
+
+# Optional Encryption
+#CUSTOM_ENCRYPT_KEY=1
+#ENCRYPT=1
+#ENCRYPT_WITH_AES256=1
+#OBJS_EXTRA=src/my_custom_encrypt_key.o
+
+# Optional QSPI debugging
+# Uncomment for verbose QSPI debug output
+#CFLAGS_EXTRA+=-DDEBUG_QSPI
+
+# Optional QSPI flash test (erase/write/read on update partition)
+# Uncomment to run test during hal_init()
+#CFLAGS_EXTRA+=-DTEST_EXT_FLASH

hal/mpfs250-hss.ld

@@ -0,0 +1,71 @@
+/* PolarFire SoC MPFS250 Linker Script for wolfBoot in L2-LIM (HSS boot)
+ *
+ * Boot sequence: HSS (eNVM/E51) loads wolfBoot into L2-LIM on U54 (S-mode).
+ * wolfBoot then loads application from SC ext SPI flash into L2-LIM.
+ * No DDR - HSS remains resident in lower L2-LIM for SBI services.
+ *
+ * Memory layout (1.5MB L2-LIM: 0x08000000 - 0x0817FFFF):
+ *   0x08000000 - HSS resident runtime (~256KB)
+ *   WOLFBOOT_ORIGIN (0x08040000) - wolfBoot code + data
+ *   WOLFBOOT_LOAD_ADDRESS (0x08060000) - Application load area
+ *   WOLFBOOT_STACK_TOP (0x08180000) - Stack grows downward
+ */
+
+OUTPUT_ARCH( "riscv" )
+
+ENTRY( _reset )
+
+MEMORY
+{
+    /* L2-LIM on-chip SRAM (cache ways configured as LIM by HSS)
+     * HSS loads wolfBoot binary here directly - no VMA/LMA split needed */
+    L2_LIM (rwx) : ORIGIN = @WOLFBOOT_ORIGIN@, LENGTH = @WOLFBOOT_L2LIM_SIZE@
+}
+
+PROVIDE(STACK_SIZE_PER_HART = 16k);
+
+SECTIONS
+{
+    .text : ALIGN(0x10)
+    {
+        _start_text = .;
+        KEEP(*(.init))
+        . = ORIGIN(L2_LIM) + 0x100;
+        _start_vector = .;
+        KEEP(*(.isr_vector))
+        . = ALIGN(0x10);
+        *(.text*)
+        *(.rodata*)
+        *(.srodata*)
+        . = ALIGN(4);
+        _end_text = .;
+    } > L2_LIM
+
+    .data : ALIGN(0x10)
+    {
+        _start_data = .;
+        KEEP(*(.ramcode*))
+        . = ALIGN(4);
+        KEEP(*(.keystore*))
+        . = ALIGN(4);
+        *(.data*)
+        . = ALIGN(4);
+        _global_pointer = . + 0x800;
+        *(.sdata*)
+        . = ALIGN(4);
+        _end_data = .;
+    } > L2_LIM
+
+    .bss (NOLOAD) : ALIGN(0x10)
+    {
+        _start_bss = .;
+        *(.bss*)
+        *(COMMON)
+        . = ALIGN(4);
+        _end_bss = .;
+        _end = .;
+    } > L2_LIM
+}
+
+PROVIDE(_start_heap = _end);
+PROVIDE(_end_stack  = ORIGIN(L2_LIM) + LENGTH(L2_LIM));

src/boot_riscv.c

@@ -510,6 +510,10 @@ void do_boot(const uint32_t *app_offset)
 #endif /* WOLFBOOT_MMODE_SMODE_BOOT */
 
 #elif __riscv_xlen == 64
+    /* Synchronize I-cache after loading new code into memory.
+     * Critical for L2-LIM where QSPI data is loaded as instructions. */
+    asm volatile("fence" ::: "memory");
+    riscv_icache_sync();
     asm volatile(
     #if defined(MMU) && !defined(WOLFBOOT_RISCV_MMODE)
         /* S-mode boot (e.g., when running under HSS/OpenSBI) */