Fixes to get DDR4 training working

Author: dgarske

config/examples/polarfire_mpfs250_m.config

@@ -115,6 +115,15 @@ CFLAGS_EXTRA+=-DSDHCI_SDMA_DISABLED
 # race on Arasan/Cadence-family controllers; single-block avoids it.
 CFLAGS_EXTRA+=-DSDHCI_FORCE_SINGLE_BLOCK_READ
 
+# MPFS250 Video Kit cache-pressure workaround: sustained PIO writes to
+# cached DDR thrash L2 cache enough to corrupt L2 Scratch (where the
+# M-mode stack lives) and cause a cause=2 epc=0 trap during the post-
+# block CMD13 wait.  OR the destination address with this alias mask so
+# PIO writes hit the non-cached DDR window (0x82000000 -> 0xC2000000)
+# and bypass L2 entirely.  Upper layers still read the buffer at the
+# cached address; L2 misses and fetches the data back from DDR.
+CFLAGS_EXTRA+=-DSDHCI_PIO_WRITE_NONCACHED_ALIAS=0x40000000UL
+
 # Video Kit routes the SD slot's Card Detect (CD#) signal through the FPGA
 # fabric rather than MSSIO, so the SDHCI controller's hardware CI/CDPL
 # detection always reads 'no card' in M-mode (no fabric configuration).
@@ -136,15 +145,14 @@ CFLAGS_EXTRA+=-DDEBUG_BOOT
 #CFLAGS_EXTRA+=-DDEBUG_SDHCI
 #CFLAGS_EXTRA+=-DDEBUG_DISK
 #CFLAGS_EXTRA+=-DDISK_TEST
-# DDR pattern test at 0x82000000 (256 KB triple-write).  This MUST
-# stay enabled -- without it the post-training MTC sanity check
-# times out and the non-cached probe hangs (the cached pattern test
-# acts as a "warm-up" that exercises the L2->DDR writeback path
-# enough to stabilize controller state).  The test halts the boot
-# after running, which is fine while disk-load is still under
-# investigation; remove the while(1) at the end of the block when
-# disk-load reliably completes.
-CFLAGS_EXTRA+=-DMPFS_DDR_PATTERN_TEST
+# DDR pattern test (256 KB triple-write at cached 0x82000000) is
+# DISABLED once disk-load works.  Its CPU writes thrash L2 cache
+# enough to corrupt L2 Scratch (where the M-mode stack lives) on the
+# return from mpfs_ddr_init().  Now that mpfs_clear_bootup_cache_ways
+# does PDMA pre-fill via the non-cached path, the pattern test is
+# redundant -- the MTC 256 B sanity inside the retry loop already
+# verifies DDR works end-to-end before pre-fill runs.
+#CFLAGS_EXTRA+=-DMPFS_DDR_PATTERN_TEST
 # Verbose register-level DDR tracing.  KEEP ENABLED until the timing
 # sensitivity in run_training is fixed -- the DBG_DDR printf delays
 # during the post-ZQ-cal phase appear to be required for TIP to

docs/Targets.md

@@ -840,7 +840,7 @@ Key build settings that differ between configurations:
 | Setting | SDCard | eMMC | QSPI | L2-LIM | M-Mode | M-Mode + DDR |
 |---------|--------|------|------|--------|--------|--------------|
 | `WOLFBOOT_ORIGIN` | `0x80000000` | `0x80000000` | `0x80000000` | `0x08040000` | `0x0A000000` | `0x0A000000` |
-| `WOLFBOOT_LOAD_ADDRESS` | `0x8E000000` | `0x8E000000` | `0x8E000000` | `0x08060000` | `0x0A010200` | `0x8E000000` |
+| `WOLFBOOT_LOAD_ADDRESS` | `0x8E000000` | `0x8E000000` | `0x8E000000` | `0x08060000` | `0x0A010200` | `0x82000000` |
 | `WOLFBOOT_LOAD_DTS_ADDRESS` | `0x8A000000` | `0x8A000000` | `0x8A000000` | – | – | `0x8A000000` |
 | `EXT_FLASH` | 0 | 0 | 1 | 1 | 1 | 0 |
 | `DISK_SDCARD` | 1 | 0 | 0 | 0 | 0 | 1 |