Peer review fixes and attempts to resolve CI compiler

Author: dgarske

arch.mk

@@ -563,11 +563,13 @@ endif
 ## RISCV (32-bit)
 ifeq ($(ARCH),RISCV)
   CROSS_COMPILE?=riscv32-unknown-elf-
-  # GCC 12+ requires explicit zicsr/zifencei extensions
-  # Note: use $(CROSS_COMPILE)gcc directly because CC is not yet defined
-  # at this point in the Makefile (it's set later in the USE_GCC block).
-  RISCV32_ZICSR := $(shell echo "" | $(CROSS_COMPILE)gcc -march=rv32imac_zicsr -x c -c - -o /dev/null 2>/dev/null && echo _zicsr)
-  RISCV32_ZIFENCEI := $(shell echo "" | $(CROSS_COMPILE)gcc -march=rv32imac_zifencei -x c -c - -o /dev/null 2>/dev/null && echo _zifencei)
+  # GCC 12-14 split CSR/fence.i into separate extensions (zicsr, zifencei)
+  # and require them explicitly. GCC 15+ re-implies them, and adding them
+  # explicitly can cause multilib lookup failures. Detect by testing if a
+  # CSR/fence.i instruction assembles WITHOUT the extension flag. If it
+  # fails, add the extension.
+  RISCV32_ZICSR := $(shell echo "void f(void){__asm__ volatile(\"csrr a0,mhartid\");}" | $(CROSS_COMPILE)gcc -march=rv32imac -mabi=ilp32 -x c -c - -o /dev/null 2>/dev/null || echo _zicsr)
+  RISCV32_ZIFENCEI := $(shell echo "void f(void){__asm__ volatile(\"fence.i\");}" | $(CROSS_COMPILE)gcc -march=rv32imac -mabi=ilp32 -x c -c - -o /dev/null 2>/dev/null || echo _zifencei)
   ARCH_FLAGS=-march=rv32imac$(RISCV32_ZICSR)$(RISCV32_ZIFENCEI) -mabi=ilp32 -mcmodel=medany
   CFLAGS+=-fno-builtin-printf -DUSE_M_TIME -g -nostartfiles -DARCH_RISCV
   CFLAGS+=$(ARCH_FLAGS)
@@ -610,12 +612,13 @@ ifeq ($(ARCH),RISCV64)
     UPDATE_OBJS?=src/update_ram.o
   endif
 
-  # GCC 12+ / binutils 2.38+ split CSR and fence.i instructions into
-  # separate extensions (zicsr, zifencei). Detect and add if supported.
-  # Note: use $(CROSS_COMPILE)gcc directly because CC is not yet defined
-  # at this point in the Makefile (it's set later in the USE_GCC block).
-  RISCV64_ZICSR := $(shell echo "" | $(CROSS_COMPILE)gcc -march=rv64imac_zicsr -x c -c - -o /dev/null 2>/dev/null && echo _zicsr)
-  RISCV64_ZIFENCEI := $(shell echo "" | $(CROSS_COMPILE)gcc -march=rv64imac_zifencei -x c -c - -o /dev/null 2>/dev/null && echo _zifencei)
+  # GCC 12-14 split CSR/fence.i into separate extensions (zicsr, zifencei)
+  # and require them explicitly. GCC 15+ re-implies them, and adding them
+  # explicitly can cause multilib lookup failures. Detect by testing if a
+  # CSR/fence.i instruction assembles WITHOUT the extension flag. If it
+  # fails, add the extension.
+  RISCV64_ZICSR := $(shell echo "void f(void){__asm__ volatile(\"csrr a0,mhartid\");}" | $(CROSS_COMPILE)gcc -march=rv64imac -mabi=lp64 -x c -c - -o /dev/null 2>/dev/null || echo _zicsr)
+  RISCV64_ZIFENCEI := $(shell echo "void f(void){__asm__ volatile(\"fence.i\");}" | $(CROSS_COMPILE)gcc -march=rv64imac -mabi=lp64 -x c -c - -o /dev/null 2>/dev/null || echo _zifencei)
 
   ifeq ($(RISCV_MMODE),1)
     # E51 core: rv64imac (no FPU, no crypto extensions)

docs/Targets.md

@@ -1444,13 +1444,14 @@ Benchmark complete
 wolfBoot supports running directly in Machine Mode (M-mode) on PolarFire SoC,
 replacing the Hart Software Services (HSS) as the first-stage bootloader. In
 M-mode, wolfBoot runs on the E51 monitor core and loads a signed application
-from SC QSPI flash to on-chip LIM (Loosely Integrated Memory).
+from SC QSPI flash to L2 Scratchpad SRAM. LIM is not used as an execute region
+due to instruction-fetch limitations (see note below).
 
 #### M-Mode Features
 
 * Runs on E51 monitor core (hart 0) directly from eNVM
 * Executes from L2 Scratchpad SRAM (256KB at 0x0A000000)
-* Loads signed application from SC QSPI flash to LIM (0x08000000)
+* Loads signed application from SC QSPI flash to L2 Scratchpad (0x0A010200)
 * No HSS or DDR required — boots entirely from on-chip memory
 * Wakes and manages secondary U54 harts via IPI
 * Per-hart UART output (each hart uses its own MMUART)

hal/mpfs250.c

@@ -1051,6 +1051,7 @@ static void qspi_uart_program(void)
 {
     uint8_t ch = 0;
     uint32_t addr, size, n_sectors, written, t;
+    uint32_t i, s;
     uint8_t chunk[QSPI_PROG_CHUNK];
 
     wolfBoot_printf("QSPI-PROG: Press 'P' within 3s to program flash\r\n");
@@ -1080,10 +1081,10 @@ static void qspi_uart_program(void)
 
     /* Receive destination address then data length (4 bytes LE each) */
     addr = 0;
-    for (int i = 0; i < 4; i++)
+    for (i = 0; i < 4; i++)
         addr |= ((uint32_t)uart_qspi_rx() << (i * 8));
     size = 0;
-    for (int i = 0; i < 4; i++)
+    for (i = 0; i < 4; i++)
         size |= ((uint32_t)uart_qspi_rx() << (i * 8));
 
     wolfBoot_printf("QSPI-PROG: addr=0x%x size=%u bytes\r\n", addr, size);
@@ -1098,7 +1099,7 @@ static void qspi_uart_program(void)
     wolfBoot_printf("QSPI-PROG: Erasing %u sector(s) at 0x%x...\r\n",
                     n_sectors, addr);
     ext_flash_unlock();
-    for (uint32_t s = 0; s < n_sectors; s++)
+    for (s = 0; s < n_sectors; s++)
         ext_flash_erase(addr + s * FLASH_SECTOR_SIZE, FLASH_SECTOR_SIZE);
 
     /* "ERASED\r\n" must be the last bytes before the first ACK (0x06).
@@ -1114,7 +1115,7 @@ static void qspi_uart_program(void)
 
         uart_qspi_tx(QSPI_PROG_ACK);          /* request next chunk */
 
-        for (uint32_t i = 0; i < chunk_len; i++)
+        for (i = 0; i < chunk_len; i++)
             chunk[i] = uart_qspi_rx();
 
         ext_flash_write(addr + written, chunk, (int)chunk_len);

src/sdhci.c

@@ -1367,10 +1367,14 @@ int sdhci_init(void)
     reg &= ~SDHCI_HRS06_EMM_MASK;
 #ifdef DISK_EMMC
     reg |= SDHCI_HRS06_MODE_LEGACY;  /* eMMC Legacy mode */
+#ifdef DEBUG_SDHCI
     wolfBoot_printf("SDHCI: eMMC mode\n");
+#endif
 #else
     reg |= SDHCI_HRS06_MODE_SD;      /* SD card mode */
+#ifdef DEBUG_SDHCI
     wolfBoot_printf("SDHCI: SDCard mode\n");
+#endif
 #endif
     SDHCI_REG_SET(SDHCI_HRS06, reg);
 
@@ -1446,15 +1450,15 @@ int sdhci_init(void)
     /* Run full eMMC card initialization */
     status = emmc_card_full_init();
     if (status != 0) {
-        wolfBoot_printf("eMMC: Card initialization failed\n");
+        wolfBoot_printf("eMMC: Card init failed (%d)\n", status);
         return status;
     }
 
 #else /* DISK_SDCARD */
     /* Run full SD card initialization */
     status = sdcard_card_full_init();
     if (status != 0) {
-        wolfBoot_printf("SD Card: Card initialization failed\n");
+        wolfBoot_printf("SD Card: Card init failed (%d)\n", status);
         return status;
     }
 
@@ -1466,6 +1470,7 @@ int sdhci_init(void)
         status = sdhci_set_timeout(SDHCI_DATA_TIMEOUT_US);
     }
 
+#ifdef DEBUG_SDHCI
     {
         const char *card_type;
 #ifdef DISK_EMMC
@@ -1475,6 +1480,7 @@ int sdhci_init(void)
 #endif
         wolfBoot_printf("sdhci_init: %s status: %d\n", card_type, status);
     }
+#endif
 
     return status;
 }

test-app/startup_riscv.c

@@ -42,10 +42,12 @@ void __attribute__((naked,section(".init"))) _reset(void) {
     asm volatile("la gp, _global_pointer");
     asm volatile("la sp, _end_stack");
 
-    /* Set up M-mode vectored interrupt table.
-     * wolfBoot M-mode does a direct jr (no enter_smode), so payload runs in M-mode.
-     * Use mtvec. The +1 sets MODE=1 (vectored). */
+    /* Set up vectored interrupt table. The +1 sets MODE=1 (vectored). */
+#ifdef WOLFBOOT_RISCV_MMODE
     asm volatile("csrw mtvec, %0":: "r"((uint8_t *)(&_start_vector) + 1));
+#else
+    asm volatile("csrw stvec, %0":: "r"((uint8_t *)(&_start_vector) + 1));
+#endif
 
     src = (uint32_t *) &_stored_data;
     dst = (uint32_t *) &_start_data;
@@ -77,8 +79,11 @@ void do_boot(const uint32_t *app_offset)
 static uint32_t synctrap_cause = 0;
 void __attribute__((naked)) isr_synctrap(void)
 {
-    /* Use mcause: payload runs in M-mode (wolfBoot does M-mode direct jump) */
+#ifdef WOLFBOOT_RISCV_MMODE
     asm volatile("csrr %0, mcause" : "=r"(synctrap_cause));
+#else
+    asm volatile("csrr %0, scause" : "=r"(synctrap_cause));
+#endif
 }
 
 void isr_empty(void)

test-app/vector_riscv.S

@@ -62,8 +62,7 @@
     ld x30, 112(sp)
     ld x31, 120(sp)
     addi sp, sp, 128
-    /* mret: payload runs in M-mode (wolfBoot does M-mode direct jump) */
-    mret
+    MODE_PREFIX(ret)
 .endm
 
 #else /* __riscv_xlen == 32 */
@@ -107,8 +106,7 @@
   lw x30, 56(sp)
   lw x31, 60(sp)
   addi sp, sp, 64
-  /* mret: payload runs in M-mode (wolfBoot does M-mode direct jump) */
-  mret
+  MODE_PREFIX(ret)
 .endm
 
 #endif /* __riscv_xlen */