Fix for BOOT_BENCHMARK=1 and timer in M-Mode. Peer review fixes.

Author: dgarske

hal/mpfs250.c

@@ -117,13 +117,14 @@ static void mpfs_config_l2_cache(void)
 
 /* Microsecond delay using busy loop.
  * MTIME counter is not running in bare-metal M-mode (no HSS), so use a
- * calibrated loop. E51 runs at ~40 MHz on reset; with volatile load/store
- * overhead each iteration is ~10 cycles → 4 iterations per microsecond.
+ * calibrated loop. E51 CPU core runs at 80 MHz on reset (2x the 40 MHz APB
+ * bus clock); with volatile load/store overhead each iteration is ~10 cycles
+ * → 8 iterations per microsecond.
  * noinline prevents the compiler from collapsing the loop at call sites. */
 static __attribute__((noinline)) void udelay(uint32_t us)
 {
     volatile uint32_t i;
-    for (i = 0; i < us * 4; i++)
+    for (i = 0; i < us * 8; i++)
         ;
 }
 

hal/mpfs250.h

@@ -27,9 +27,9 @@
 
 /* PolarFire SoC MPFS250T board specific configuration */
 
-/* APB/AHB Clock Frequency
- * M-mode (out of reset): 40 MHz
- * S-mode (after HSS): 150 MHz
+/* APB/AHB Peripheral Bus Clock Frequency (used for UART baud rate divisor)
+ * M-mode (out of reset, no PLL): 40 MHz
+ * S-mode (after HSS configures PLL): 150 MHz
  */
 #ifndef MSS_APB_AHB_CLK
     #ifdef WOLFBOOT_RISCV_MMODE
@@ -39,6 +39,17 @@
     #endif
 #endif
 
+/* CPU Core Clock Frequency (used for mcycle-based benchmarking)
+ * The E51 core runs at 2x the APB bus clock on reset.
+ * After HSS configures the PLL, CPU runs at 600 MHz. */
+#ifndef MSS_CPU_CLK
+    #ifdef WOLFBOOT_RISCV_MMODE
+        #define MSS_CPU_CLK         (MSS_APB_AHB_CLK * 2)
+    #else
+        #define MSS_CPU_CLK         600000000
+    #endif
+#endif
+
 /* Hardware Base Address */
 #define SYSREG_BASE 0x20002000
 
@@ -327,6 +338,14 @@ int mpfs_read_serial_number(uint8_t *serial);
 /* RTC Clock Frequency (1 MHz after divisor) */
 #define RTC_CLOCK_FREQ              1000000UL
 
+/* Timer frequency for hal_get_timer_us().
+ * In M-mode: CLINT MTIME is not running without HSS, so hal_get_timer()
+ * reads mcycle (CPU cycle counter) instead. Set frequency to CPU clock.
+ * In S-mode: MTIME runs at 1 MHz (default RISCV_SMODE_TIMER_FREQ). */
+#if defined(WOLFBOOT_RISCV_MMODE) && !defined(RISCV_SMODE_TIMER_FREQ)
+#define RISCV_SMODE_TIMER_FREQ      MSS_CPU_CLK
+#endif
+
 
 /* ============================================================================
  * Hart Local Storage (HLS) - Per-hart communication structure

src/boot_riscv.c

@@ -207,8 +207,14 @@ unsigned long WEAKFUNCTION handle_trap(unsigned long cause, unsigned long epc,
 
 uint64_t hal_get_timer(void)
 {
-#if __riscv_xlen == 64
-    /* For RV64, CSR time contains full 64-bit value */
+#ifdef WOLFBOOT_RISCV_MMODE
+    /* In M-mode, use mcycle (CPU cycle counter) instead of rdtime/CLINT MTIME.
+     * rdtime CSR causes illegal instruction on E51 in bare-metal M-mode, and
+     * CLINT MTIME is not running without HSS. mcycle always increments at the
+     * CPU clock rate (MSS_APB_AHB_CLK). */
+    return csr_read(mcycle);
+#elif __riscv_xlen == 64
+    /* For RV64 S-mode, CSR time contains full 64-bit value */
     return csr_read(time);
 #else
     /* For RV32, read both timeh and time with wrap-around protection */

test-app/startup_riscv.c

@@ -42,31 +42,6 @@ void __attribute__((naked,section(".init"))) _reset(void) {
     asm volatile("la gp, _global_pointer");
     asm volatile("la sp, _end_stack");
 
-    /* Direct UART diagnostic: write "!\r\n" to confirm test-app is running.
-     * MPFS MMUART: THR at offset 0x100, LSR at offset 0x14, THRE = bit 5. */
-    asm volatile(
-        "li a0, 0x20000000\n"    /* UART0 base */
-        /* write '!' */
-        "1: lbu a1, 0x14(a0)\n"  /* read LSR */
-        "andi a1, a1, 0x20\n"    /* check THRE (bit 5) */
-        "beqz a1, 1b\n"
-        "li a2, 0x21\n"          /* '!' */
-        "sb a2, 0x100(a0)\n"     /* write to THR */
-        /* write '\r' */
-        "2: lbu a1, 0x14(a0)\n"
-        "andi a1, a1, 0x20\n"
-        "beqz a1, 2b\n"
-        "li a2, 0x0d\n"          /* '\r' */
-        "sb a2, 0x100(a0)\n"
-        /* write '\n' */
-        "3: lbu a1, 0x14(a0)\n"
-        "andi a1, a1, 0x20\n"
-        "beqz a1, 3b\n"
-        "li a2, 0x0a\n"          /* '\n' */
-        "sb a2, 0x100(a0)\n"
-        ::: "a0", "a1", "a2"
-    );
-
     /* Set up M-mode vectored interrupt table.
      * wolfBoot M-mode does a direct jr (no enter_smode), so payload runs in M-mode.
      * Use mtvec. The +1 sets MODE=1 (vectored). */