Fixes for NXP T2080 ports

.github/workflows/test-configs.yml

@@ -211,6 +211,24 @@ jobs:
       arch: ppc
       config-file: ./config/examples/nxp-t2080.config
 
+  # Additional T2080 board-specific compile tests for alternate board macros.
+  nxp_t2080_test_naii_68ppc2:
+    uses: ./.github/workflows/test-build-powerpc.yml
+    with:
+      arch: ppc
+      config-file: ./config/examples/nxp-t2080.config
+      make-args: CFLAGS_EXTRA=-DBOARD_NAII_68PPC2
+
+  # VPX3-152 compile test: validates board-specific code paths build cleanly.
+  # Uses default config addresses (128MB layout); real hardware needs the
+  # VPX3-152 address overrides uncommented in .config.
+  nxp_t2080_vpx3152_test:
+    uses: ./.github/workflows/test-build-powerpc.yml
+    with:
+      arch: ppc
+      config-file: ./config/examples/nxp-t2080.config
+      make-args: CFLAGS_EXTRA=-DBOARD_CW_VPX3152
+
   nxp_ls1028a_test:
     uses: ./.github/workflows/test-build.yml
     with:

config/examples/nxp-t2080.config

@@ -1,13 +1,17 @@
 # NXP T2080 wolfBoot Configuration
 # Default board: T2080 RDB (66.66 MHz oscillator, DDR3L SODIMM)
 #
-# Board selection: uncomment exactly one line to override the default.
-#   Default (no define): T2080 RDB (66.66 MHz oscillator, DDR3L SODIMM)
-#   BOARD_CW_VPX3152:   CW VPX3-152 (66.667 MHz oscillator, DDR3L)
-#   BOARD_NAII_68PPC2:  NAII 68PPC2 (100 MHz oscillator, 8GB DDR3)
+# Board selection:
+#   Default (no define):  T2080 RDB (66.66 MHz oscillator, DDR3L SODIMM)
+#   BOARD_NAII_68PPC2:    NAII 68PPC2 (100 MHz oscillator, 8 GB DDR3)
+#   BOARD_CW_VPX3152:     CW VPX3-152 (66.667 MHz oscillator, 4 GB DDR3L)
 #
-#CFLAGS_EXTRA+=-DBOARD_CW_VPX3152
+# For NAII 68PPC2, uncomment the line below (addresses are the same as RDB):
 #CFLAGS_EXTRA+=-DBOARD_NAII_68PPC2
+#
+# For CW VPX3-152 (256 MB NOR flash at 0xF0000000), uncomment the BOARD
+# define AND the address override block at the bottom of this file.
+#CFLAGS_EXTRA+=-DBOARD_CW_VPX3152
 
 ARCH=PPC
 TARGET=nxp_t2080
@@ -35,50 +39,57 @@ DUALBANK_SWAP?=0
 WOLFTPM?=0
 OPTIMIZATION_LEVEL?=1
 
-# NOR Base Address
-# T2080 RDB:   128MB flash at 0xE8000000, wolfBoot at top (0xEFFE0000)
-# CW VPX3-152: 256MB flash at 0xF0000000, wolfBoot at top (0xFFFE0000)
+# -----------------------------------------------------------------------------
+# Default addresses: T2080 RDB / NAII 68PPC2 (128 MB NOR flash @ 0xE8000000)
+# -----------------------------------------------------------------------------
+
+# NOR Base Address: wolfBoot at top of flash
 ARCH_FLASH_OFFSET?=0xEFFE0000
-#ARCH_FLASH_OFFSET?=0xFFFE0000  # CW VPX3-152
 
 # CPC SRAM address (must match L2SRAM_ADDR in nxp_ppc.h)
-# CW VPX3-152: relocated to 0xEE900000 to avoid 256MB flash TLB overlap
 L2SRAM_ADDR?=0xF8F00000
-#L2SRAM_ADDR?=0xEE900000  # CW VPX3-152
 
 # Flash Sector Size
 WOLFBOOT_SECTOR_SIZE?=0x10000
 
 # wolfBoot start address
 WOLFBOOT_ORIGIN?=0xEFFE0000
-#WOLFBOOT_ORIGIN?=0xFFFE0000  # CW VPX3-152
 # wolfBoot partition size (custom)
 BOOTLOADER_PARTITION_SIZE=0x20000
 
 # Application Partition Size
 WOLFBOOT_PARTITION_SIZE?=0x100000
 # Location in Flash for Application Partition
 WOLFBOOT_PARTITION_BOOT_ADDRESS?=0xEFEE0000
-#WOLFBOOT_PARTITION_BOOT_ADDRESS?=0xFFEE0000  # CW VPX3-152
 # Load Partition to RAM Address
 WOLFBOOT_LOAD_ADDRESS?=0x19000
 
 # Location in Flash for Update Partition
 WOLFBOOT_PARTITION_UPDATE_ADDRESS?=0xEFDE0000
-#WOLFBOOT_PARTITION_UPDATE_ADDRESS?=0xFFDE0000  # CW VPX3-152
 
 # Location of temporary sector used during updates
 WOLFBOOT_PARTITION_SWAP_ADDRESS?=0xEFDD0000
-#WOLFBOOT_PARTITION_SWAP_ADDRESS?=0xFFDD0000  # CW VPX3-152
 
 # DTS (Device Tree)
 WOLFBOOT_DTS_BOOT_ADDRESS?=0xE8040000
-#WOLFBOOT_DTS_BOOT_ADDRESS?=0xF0040000  # CW VPX3-152
 WOLFBOOT_DTS_UPDATE_ADDRESS?=0xE8050000
-#WOLFBOOT_DTS_UPDATE_ADDRESS?=0xF0050000  # CW VPX3-152
 # DTS Load to RAM Address
 WOLFBOOT_LOAD_DTS_ADDRESS?=0x200000
 
+# -----------------------------------------------------------------------------
+# CW VPX3-152 address overrides (256 MB NOR flash @ 0xF0000000)
+# Uncomment ALL lines below when building for VPX3-152.
+# Also uncomment CFLAGS_EXTRA+=-DBOARD_CW_VPX3152 at the top of this file.
+# -----------------------------------------------------------------------------
+#ARCH_FLASH_OFFSET=0xFFFE0000
+#L2SRAM_ADDR=0xEE900000
+#WOLFBOOT_ORIGIN=0xFFFE0000
+#WOLFBOOT_PARTITION_BOOT_ADDRESS=0xFFEE0000
+#WOLFBOOT_PARTITION_UPDATE_ADDRESS=0xFFDE0000
+#WOLFBOOT_PARTITION_SWAP_ADDRESS=0xFFDD0000
+#WOLFBOOT_DTS_BOOT_ADDRESS=0xF0040000
+#WOLFBOOT_DTS_UPDATE_ADDRESS=0xF0050000
+
 # Flash erase/write/read test at update partition address
 #TEST_FLASH?=1