[clock, tests, docs] Remove GetRate from clock device type

Author: AlexLanzano

docs/writing_a_driver.md

@@ -332,12 +332,6 @@ driver should handle all of these.
 Disable a peripheral clock gate. The inverse of Enable — clear the enable bit(s)
 for the given clock descriptor.
 
-### GetRate
-
-Report the current system clock frequency in Hz. The driver should compute this
-from the configured source, PLL coefficients, and divider settings. Store the
-result in the output pointer.
-
 ---
 
 ## GPIO

src/clock/clock.c

@@ -37,14 +37,3 @@ inline whal_Error whal_Clock_Disable(whal_Clock *clkDev, const void *clk)
     return clkDev->driver->Disable(clkDev, clk);
 }
 
-inline whal_Error whal_Clock_GetRate(whal_Clock *clkDev, size_t *rateOut)
-{
-    if (!clkDev || !clkDev->driver || !clkDev->driver->GetRate ||
-        !rateOut) 
-    {
-        return WHAL_EINVAL;
-    }
-
-    return clkDev->driver->GetRate(clkDev, rateOut);
-}
-

src/clock/pic32cz_clock.c

@@ -238,21 +238,9 @@ whal_Error whal_Pic32czClock_Disable(whal_Clock *clkDev, const void *clk)
     return WHAL_SUCCESS;
 }
 
-whal_Error whal_Pic32czClock_GetRate(whal_Clock *clkDev, size_t *rateOut)
-{
-    if (!clkDev || !rateOut) {
-        return WHAL_EINVAL;
-    }
-
-    /* TODO: Calculate actual clock rate from PLL and divider settings */
-    *rateOut = 0;
-    return WHAL_SUCCESS;
-}
-
 const whal_ClockDriver whal_Pic32czClockPll_Driver = {
     .Init = whal_Pic32czClockPll_Init,
     .Deinit = whal_Pic32czClockPll_Deinit,
     .Enable = whal_Pic32czClock_Enable,
     .Disable = whal_Pic32czClock_Disable,
-    .GetRate = whal_Pic32czClock_GetRate,
 };

src/clock/stm32c0_rcc.c

@@ -114,26 +114,9 @@ whal_Error whal_Stm32c0Rcc_Disable(whal_Clock *clkDev, const void *clk)
     return WHAL_SUCCESS;
 }
 
-whal_Error whal_Stm32c0Rcc_GetRate(whal_Clock *clkDev, size_t *rateOut)
-{
-    whal_Stm32c0Rcc_Cfg *cfg;
-
-    if (!clkDev || !clkDev->cfg || !rateOut) {
-        return WHAL_EINVAL;
-    }
-
-    cfg = (whal_Stm32c0Rcc_Cfg *)clkDev->cfg;
-
-    /* HSI48 base frequency divided by HSIDIV (1 << hsidiv) */
-    *rateOut = 48000000 / (1 << cfg->hsidiv);
-
-    return WHAL_SUCCESS;
-}
-
 const whal_ClockDriver whal_Stm32c0Rcc_Driver = {
     .Init = whal_Stm32c0Rcc_Init,
     .Deinit = whal_Stm32c0Rcc_Deinit,
     .Enable = whal_Stm32c0Rcc_Enable,
     .Disable = whal_Stm32c0Rcc_Disable,
-    .GetRate = whal_Stm32c0Rcc_GetRate,
 };

src/clock/stm32f4_rcc.c

@@ -72,9 +72,6 @@
 #define RCC_CFGR_PPRE2_Pos 13
 #define RCC_CFGR_PPRE2_Msk (WHAL_BITMASK(3) << RCC_CFGR_PPRE2_Pos)
 
-/* PLLP register value to actual divider: 0->2, 1->4, 2->6, 3->8 */
-static const uint8_t pllp_div[] = { 2, 4, 6, 8 };
-
 whal_Error whal_Stm32f4RccPll_Init(whal_Clock *clkDev)
 {
     whal_Stm32f4Rcc_Cfg *cfg;
@@ -211,39 +208,9 @@ whal_Error whal_Stm32f4Rcc_Disable(whal_Clock *clkDev, const void *clk)
     return WHAL_SUCCESS;
 }
 
-whal_Error whal_Stm32f4RccPll_GetRate(whal_Clock *clkDev, size_t *rateOut)
-{
-    whal_Stm32f4Rcc_Cfg *cfg;
-    whal_Stm32f4Rcc_PllClkCfg *pllCfg;
-    size_t srcFreq;
-    size_t pllm;
-    size_t plln;
-    size_t pllp;
-
-    if (!clkDev || !clkDev->cfg || !rateOut)
-        return WHAL_EINVAL;
-
-    cfg = (whal_Stm32f4Rcc_Cfg *)clkDev->cfg;
-    pllCfg = (whal_Stm32f4Rcc_PllClkCfg *)cfg->sysClkCfg;
-
-    /* Determine source frequency */
-    if (pllCfg->clkSrc == WHAL_STM32F4_RCC_PLLCLK_SRC_HSI)
-        srcFreq = 16000000;
-    else
-        srcFreq = 25000000;
-
-    pllm = pllCfg->m;
-    plln = pllCfg->n;
-    pllp = pllp_div[pllCfg->p & 0x3];
-
-    *rateOut = ((srcFreq / pllm) * plln) / pllp;
-    return WHAL_SUCCESS;
-}
-
 const whal_ClockDriver whal_Stm32f4RccPll_Driver = {
     .Init = whal_Stm32f4RccPll_Init,
     .Deinit = whal_Stm32f4RccPll_Deinit,
     .Enable = whal_Stm32f4Rcc_Enable,
     .Disable = whal_Stm32f4Rcc_Disable,
-    .GetRate = whal_Stm32f4RccPll_GetRate,
 };

src/clock/stm32h5_rcc.c

@@ -102,29 +102,6 @@
 /* HSI base frequency */
 #define HSI_FREQ 64000000UL
 
-/*
- * Compute the input reference frequency for PLL source selection.
- * Returns the HSI frequency accounting for the divider if HSI is selected.
- */
-static size_t Stm32h5Rcc_GetPllInputFreq(size_t rccBase,
-                                          whal_Stm32h5Rcc_PllClockSrc src)
-{
-    size_t hsidiv;
-
-    switch (src) {
-    case WHAL_STM32H5_RCC_PLLCLK_SRC_HSI:
-        whal_Reg_Get(rccBase, RCC_CR_REG, RCC_CR_HSIDIV_Msk,
-                     RCC_CR_HSIDIV_Pos, &hsidiv);
-        return HSI_FREQ >> hsidiv;
-    case WHAL_STM32H5_RCC_PLLCLK_SRC_CSI:
-        return 4000000;
-    case WHAL_STM32H5_RCC_PLLCLK_SRC_HSE:
-        return 8000000; /* TODO: Make configurable per board */
-    default:
-        return 0;
-    }
-}
-
 whal_Error whal_Stm32h5RccPll_Init(whal_Clock *clkDev)
 {
     whal_Stm32h5Rcc_Cfg *cfg;
@@ -333,71 +310,18 @@ whal_Error whal_Stm32h5Rcc_Disable(whal_Clock *clkDev, const void *clk)
     return WHAL_SUCCESS;
 }
 
-whal_Error whal_Stm32h5RccPll_GetRate(whal_Clock *clkDev, size_t *rateOut)
-{
-    whal_Stm32h5Rcc_Cfg *cfg;
-    whal_Stm32h5Rcc_PllClkCfg *pllCfg;
-    size_t srcFreq;
-    size_t pllm;
-    size_t plln;
-    size_t pllp;
-
-    if (!clkDev || !clkDev->cfg || !rateOut)
-        return WHAL_EINVAL;
-
-    cfg = (whal_Stm32h5Rcc_Cfg *)clkDev->cfg;
-    pllCfg = (whal_Stm32h5Rcc_PllClkCfg *)cfg->sysClkCfg;
-
-    srcFreq = Stm32h5Rcc_GetPllInputFreq(clkDev->regmap.base, pllCfg->clkSrc);
-    if (srcFreq == 0)
-        return WHAL_EINVAL;
-
-    /*
-     * PLL1 output (pll1_p_ck):
-     *   f_vco = (f_src / m) * (n + 1)
-     *   f_pllp = f_vco / (p + 1)
-     *
-     * PLL1M: register value is the divisor directly (1-63, 0=disabled)
-     * PLL1N: register value + 1 is the multiplier (3=4x, 4=5x, ...)
-     * PLL1P: register value + 1 is the divisor (1=/2, 2=/3, ...)
-     */
-    pllm = pllCfg->m;
-    plln = pllCfg->n + 1;
-    pllp = pllCfg->p + 1;
-
-    *rateOut = ((srcFreq / pllm) * plln) / pllp;
-    return WHAL_SUCCESS;
-}
-
-whal_Error whal_Stm32h5RccHsi_GetRate(whal_Clock *clkDev, size_t *rateOut)
-{
-    size_t hsidiv;
-
-    if (!clkDev || !rateOut)
-        return WHAL_EINVAL;
-
-    whal_Reg_Get(clkDev->regmap.base, RCC_CR_REG, RCC_CR_HSIDIV_Msk,
-                 RCC_CR_HSIDIV_Pos, &hsidiv);
-
-    /* HSI divider: 0=div1(64MHz), 1=div2(32MHz), 2=div4(16MHz), 3=div8(8MHz) */
-    *rateOut = HSI_FREQ >> hsidiv;
-    return WHAL_SUCCESS;
-}
-
 const whal_ClockDriver whal_Stm32h5RccPll_Driver = {
     .Init = whal_Stm32h5RccPll_Init,
     .Deinit = whal_Stm32h5RccPll_Deinit,
     .Enable = whal_Stm32h5Rcc_Enable,
     .Disable = whal_Stm32h5Rcc_Disable,
-    .GetRate = whal_Stm32h5RccPll_GetRate,
 };
 
 const whal_ClockDriver whal_Stm32h5RccHsi_Driver = {
     .Init = whal_Stm32h5RccHsi_Init,
     .Deinit = whal_Stm32h5RccHsi_Deinit,
     .Enable = whal_Stm32h5Rcc_Enable,
     .Disable = whal_Stm32h5Rcc_Disable,
-    .GetRate = whal_Stm32h5RccHsi_GetRate,
 };
 
 whal_Error whal_Stm32h5Rcc_Ext_EnableHsi48(whal_Clock *clkDev, uint8_t enable)

src/clock/stm32wb_rcc.c

@@ -262,93 +262,6 @@ whal_Error whal_Stm32wbRcc_Disable(whal_Clock *clkDev, const void *clk)
     return WHAL_SUCCESS;
 }
 
-whal_Error whal_Stm32wbRccPll_GetRate(whal_Clock *clkDev, size_t *rateOut)
-{
-    whal_Stm32wbRcc_Cfg *cfg;
-
-    if (!clkDev || !clkDev->cfg) {
-        return WHAL_EINVAL;
-    }
-
-    cfg = (whal_Stm32wbRcc_Cfg *)clkDev->cfg;
-    whal_Stm32wbRcc_PllClkCfg *pllClkCfg = cfg->sysClkCfg;
-
-    /*
-     * Calculate PLL output frequency:
-     *   f_pllr = ((f_src / (m + 1)) * n) / (r + 1)
-     */
-    size_t srcFreq;
-    size_t pllm = pllClkCfg->m + 1;
-    size_t plln = pllClkCfg->n;
-    size_t pllr = pllClkCfg->r + 1;
-
-    /* Determine source frequency based on PLL input selection */
-    if (pllClkCfg->clkSrc == WHAL_STM32WB_RCC_PLLCLK_SRC_MSI) {
-        srcFreq = 4000000;
-    }
-    else {
-        return WHAL_EINVAL;
-    }
-
-    *rateOut = ((srcFreq / pllm) * plln) / pllr;
-    return WHAL_SUCCESS;
-}
-
-whal_Error whal_Stm32wbRccMsi_GetRate(whal_Clock *clkDev, size_t *rateOut)
-{
-    size_t msiRange;
-
-    if (!clkDev || !rateOut) {
-        return WHAL_EINVAL;
-    }
-
-    /* Read current MSI range from hardware */
-    whal_Reg_Get(clkDev->regmap.base, RCC_CR_REG, RCC_CR_MSIRANGE_Msk,
-                 RCC_CR_MSIRANGE_Pos, &msiRange);
-
-    /* Map range setting to frequency in Hz */
-    switch (msiRange) {
-    case WHAL_STM32WB_RCC_MSIRANGE_100kHz:
-        *rateOut = 100000;
-        break;
-    case WHAL_STM32WB_RCC_MSIRANGE_200kHz:
-        *rateOut = 200000;
-        break;
-    case WHAL_STM32WB_RCC_MSIRANGE_400kHz:
-        *rateOut = 400000;
-        break;
-    case WHAL_STM32WB_RCC_MSIRANGE_800kHz:
-        *rateOut = 800000;
-        break;
-    case WHAL_STM32WB_RCC_MSIRANGE_1MHz:
-        *rateOut = 1000000;
-        break;
-    case WHAL_STM32WB_RCC_MSIRANGE_2MHz:
-        *rateOut = 2000000;
-        break;
-    case WHAL_STM32WB_RCC_MSIRANGE_4MHz:
-        *rateOut = 4000000;
-        break;
-    case WHAL_STM32WB_RCC_MSIRANGE_8MHz:
-        *rateOut = 8000000;
-        break;
-    case WHAL_STM32WB_RCC_MSIRANGE_16MHz:
-        *rateOut = 16000000;
-        break;
-    case WHAL_STM32WB_RCC_MSIRANGE_24MHz:
-        *rateOut = 24000000;
-        break;
-    case WHAL_STM32WB_RCC_MSIRANGE_32MHz:
-        *rateOut = 32000000;
-        break;
-    case WHAL_STM32WB_RCC_MSIRANGE_48MHz:
-        *rateOut = 48000000;
-        break;
-    }
-
-    return WHAL_SUCCESS;
-}
-
 whal_Error whal_Stm32wbRcc_Ext_EnableHsi48(whal_Clock *clkDev, uint8_t enable)
 {
     if (!clkDev) {
@@ -394,13 +307,11 @@ const whal_ClockDriver whal_Stm32wbRccPll_Driver = {
     .Deinit = whal_Stm32wbRccPll_Deinit,
     .Enable = whal_Stm32wbRcc_Enable,
     .Disable = whal_Stm32wbRcc_Disable,
-    .GetRate = whal_Stm32wbRccPll_GetRate,
 };
 
 const whal_ClockDriver whal_Stm32wbRccMsi_Driver = {
     .Init = whal_Stm32wbRccMsi_Init,
     .Deinit = whal_Stm32wbRccMsi_Deinit,
     .Enable = whal_Stm32wbRcc_Enable,
     .Disable = whal_Stm32wbRcc_Disable,
-    .GetRate = whal_Stm32wbRccMsi_GetRate,
 };

tests/clock/test_clock.c

@@ -4,27 +4,15 @@
 
 static void Test_Clock_Api(void)
 {
-    size_t rate;
-
     WHAL_ASSERT_EQ(whal_Clock_Init(NULL), WHAL_EINVAL);
     WHAL_ASSERT_EQ(whal_Clock_Deinit(NULL), WHAL_EINVAL);
     WHAL_ASSERT_EQ(whal_Clock_Enable(NULL, NULL), WHAL_EINVAL);
     WHAL_ASSERT_EQ(whal_Clock_Disable(NULL, NULL), WHAL_EINVAL);
-    WHAL_ASSERT_EQ(whal_Clock_GetRate(NULL, &rate), WHAL_EINVAL);
-    WHAL_ASSERT_EQ(whal_Clock_GetRate(&g_whalClock, NULL), WHAL_EINVAL);
-}
-
-static void Test_Clock_GetRate(void)
-{
-    size_t rate = 0;
-    WHAL_ASSERT_EQ(whal_Clock_GetRate(&g_whalClock, &rate), WHAL_SUCCESS);
-    WHAL_ASSERT_NEQ(rate, 0);
 }
 
 void whal_Test_Clock(void)
 {
     WHAL_TEST_SUITE_START("clock");
     WHAL_TEST(Test_Clock_Api);
-    WHAL_TEST(Test_Clock_GetRate);
     WHAL_TEST_SUITE_END();
 }

tests/core/test_dispatch.c

@@ -13,14 +13,11 @@ static whal_Error MockClockInit(whal_Clock *d) { (void)d; return WHAL_SUCCESS; }
 static whal_Error MockClockDeinit(whal_Clock *d) { (void)d; return WHAL_SUCCESS; }
 static whal_Error MockClockEnable(whal_Clock *d, const void *c) { (void)d; (void)c; return WHAL_SUCCESS; }
 static whal_Error MockClockDisable(whal_Clock *d, const void *c) { (void)d; (void)c; return WHAL_SUCCESS; }
-static whal_Error MockClockGetRate(whal_Clock *d, size_t *r) { (void)d; *r = 64000000; return WHAL_SUCCESS; }
-
 static const whal_ClockDriver mockClockDriver = {
     .Init = MockClockInit,
     .Deinit = MockClockDeinit,
     .Enable = MockClockEnable,
     .Disable = MockClockDisable,
-    .GetRate = MockClockGetRate,
 };
 
 static whal_Error MockGpioInit(whal_Gpio *d) { (void)d; return WHAL_SUCCESS; }
@@ -109,8 +106,6 @@ static void Test_Clock_NullDev(void)
     WHAL_ASSERT_EQ(whal_Clock_Deinit(NULL), WHAL_EINVAL);
     WHAL_ASSERT_EQ(whal_Clock_Enable(NULL, NULL), WHAL_EINVAL);
     WHAL_ASSERT_EQ(whal_Clock_Disable(NULL, NULL), WHAL_EINVAL);
-    size_t rate;
-    WHAL_ASSERT_EQ(whal_Clock_GetRate(NULL, &rate), WHAL_EINVAL);
 }
 
 static void Test_Clock_NullDriver(void)
@@ -133,9 +128,6 @@ static void Test_Clock_ValidDispatch(void)
     WHAL_ASSERT_EQ(whal_Clock_Deinit(&dev), WHAL_SUCCESS);
     WHAL_ASSERT_EQ(whal_Clock_Enable(&dev, NULL), WHAL_SUCCESS);
     WHAL_ASSERT_EQ(whal_Clock_Disable(&dev, NULL), WHAL_SUCCESS);
-    size_t rate;
-    WHAL_ASSERT_EQ(whal_Clock_GetRate(&dev, &rate), WHAL_SUCCESS);
-    WHAL_ASSERT_EQ(rate, 64000000);
 }
 
 /* --- GPIO dispatch tests --- */