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versal: bare-metal wolfIP port for Versal Gen 1 (Cortex-A72 EL3)
VMK180 bring-up reusing ~90% of the ZCU102 port: A72 at EL3, GICv3, PL011 console, Cadence GEM0 + DP83867. Platform comes up from the PLM (boot PDI over JTAG); the GEM reference clock is left to the PLM (Versal CRL is PMC-protected). Poll-driven RX, all-address PHY scan preferring the linked PHY. HW-tested on a VMK180: DHCP + ping + UDP echo.
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‎src/port/versal/.gitignore‎

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*.o
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*.elf
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*.bin
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BOOT.BIN
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.layout_stamp

‎src/port/versal/Makefile‎

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# Xilinx Versal Gen 1 (VMK180, Cortex-A72) wolfIP bare-metal port
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#
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# Build: make CROSS_COMPILE=aarch64-none-elf-
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#
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# Toolchain: ARM GNU aarch64-none-elf-gcc (tested with 14.3.rel1).
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#
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# UNTESTED ON HARDWARE -- structural scaffold mirroring src/port/zcu102/.
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CROSS_COMPILE ?= aarch64-none-elf-
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CC := $(CROSS_COMPILE)gcc
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OBJCOPY := $(CROSS_COMPILE)objcopy
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SIZE := $(CROSS_COMPILE)size
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ROOT := ../../..
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# Cortex-A72, AArch64, EL3 single-EL bare-metal. No SIMD/FP in the
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# wolfIP/driver paths - keep -mgeneral-regs-only to catch any
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# accidental FP use and make the ABI deterministic for cert.
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CFLAGS := -mcpu=cortex-a72 -mgeneral-regs-only
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CFLAGS += -Os -ffreestanding -fno-builtin -fno-common
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CFLAGS += -fdata-sections -ffunction-sections
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CFLAGS += -g -Wall -Wextra -Werror -Wno-unused-parameter
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CFLAGS += -std=gnu99
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CFLAGS += -I. -I$(ROOT) -I$(ROOT)/src -I$(ROOT)/src/port
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CFLAGS += -DVERSAL -DXILINX_AARCH64
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# Append extra defines for investigation builds, e.g.:
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# make CFLAGS_EXTRA="-DDEBUG_GIC -DDEBUG_GEM -DDEBUG_PHY"
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CFLAGS += $(CFLAGS_EXTRA)
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ASFLAGS := -mcpu=cortex-a72
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# Layout selector. Default ocm keeps the OCM-only layout that the JTAG
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# iteration scripts depend on (everything in OCM @ 0xFFFC0000). Pass
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# LAYOUT=ddr to relink for DDR @ 0x10000000 -- which is what wolfBoot
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# uses (WOLFBOOT_LOAD_ADDRESS in zynqmp.config also applies to Versal
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# when adapted).
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LAYOUT ?= ocm
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ifeq ($(LAYOUT),ddr)
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LDSCRIPT := target_ddr.ld
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CFLAGS += -DVERSAL_LAYOUT_DDR
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else ifeq ($(LAYOUT),ocm)
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LDSCRIPT := target.ld
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CFLAGS += -DVERSAL_LAYOUT_OCM
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else
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$(error LAYOUT must be 'ocm' or 'ddr')
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endif
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LDFLAGS := -nostdlib -nostartfiles -T $(LDSCRIPT) -Wl,-gc-sections
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# Replace newlib's aarch64 memset/memcpy (which use 'dc zva' and may
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# hang on a similar Cortex-A72 setup; the safe pattern is to override
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# them as we did on ZCU102).
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LDFLAGS += -Wl,--wrap=memset -Wl,--wrap=memcpy
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LOCAL_C := main.c uart.c mmu.c gic.c gem.c phy_dp83867.c entropy.c
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LOCAL_S := startup.S
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LOCAL_OBJS := $(LOCAL_C:.c=.o) $(LOCAL_S:.S=.o)
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WOLFIP_OBJ := wolfip.o
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OBJS := $(LOCAL_OBJS) $(WOLFIP_OBJ)
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# Keep 'all' the default goal even though the layout-stamp rules below
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# are defined before it.
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.DEFAULT_GOAL := all
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# A change in LAYOUT must force a full rebuild: OCM objects link against
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# 0xFFFC0000 and a DDR build against 0x10000000, so reusing stale objects
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# across a layout switch silently produces a wrong image. The stamp
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# records the last LAYOUT; its mtime only bumps when LAYOUT actually
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# changes, so same-layout incremental builds are unaffected.
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LAYOUT_STAMP := .layout_stamp
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.PHONY: FORCE
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FORCE:
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$(LAYOUT_STAMP): FORCE
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@if [ "`cat $@ 2>/dev/null`" != "$(LAYOUT)" ]; then \
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echo "LAYOUT -> $(LAYOUT) (was `cat $@ 2>/dev/null`); forcing rebuild"; \
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echo "$(LAYOUT)" > $@; \
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fi
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$(OBJS): $(LAYOUT_STAMP)
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all: app.elf
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@echo "Built: app.elf"
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@$(SIZE) app.elf
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app.elf: $(OBJS) $(LDSCRIPT)
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$(CC) $(CFLAGS) $(OBJS) $(LDFLAGS) \
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-Wl,--start-group -lc -lgcc -Wl,--end-group -o $@
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$(WOLFIP_OBJ): $(ROOT)/src/wolfip.c
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$(CC) $(CFLAGS) -Wno-zero-length-bounds -Wno-type-limits -c $< -o $@
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%.o: %.c
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$(CC) $(CFLAGS) -c $< -o $@
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%.o: %.S
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$(CC) $(ASFLAGS) -c $< -o $@
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clean:
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rm -f $(OBJS) app.elf BOOT.BIN $(LAYOUT_STAMP)
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.PHONY: all clean help
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help:
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@echo "Versal Gen 1 wolfIP build (scaffold, untested):"
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@echo " make - build app.elf (OCM layout)"
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@echo " make LAYOUT=ddr - DDR layout for wolfBoot"
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@echo " make clean - remove artifacts"
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@echo ""
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@echo "Override CROSS_COMPILE if your toolchain prefix differs."

‎src/port/versal/README.md‎

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# wolfIP port: Xilinx Versal Gen 1 (VMK180)
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**STATUS: brought up on a VMK180.** DHCP, ICMP ping and the UDP echo demo all work on real hardware (Cortex-A72 EL3, GEM0 + DP83867). See "Hardware bring-up notes" below for the Versal-specific differences.
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## What this port is
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Bare-metal wolfIP port for the AMD/Xilinx Versal ACAP Gen 1, demoed on the VMK180 dev board. Cortex-A72 APU 0 at EL3, GCC bare-metal, no Xilinx Standalone BSP, no FreeRTOS. Targets the same deterministic UDP/IPv4 profile as the ZCU102 port for DO-178C DAL-C qualification.
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## What differs from ZCU102
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| Subsystem | ZCU102 | Versal Gen 1 | Where it lives |
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|-----------|--------|--------------|----------------|
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| APU core | Cortex-A53 | Cortex-A72 | `Makefile` (-mcpu) |
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| Bootloader handoff | FSBL -> EL3 | PLM -> BL31 -> EL3 (or EL2) | `startup.S` |
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| GIC | GIC-400 (GICv2) | GIC-600 (GICv3) | `gic.c` rewritten for GICv3 system regs + GICR |
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| UART | Cadence | ARM PL011 | `uart.c` rewritten |
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| GEM count | 4 (GEM0-3) | 2 (GEM0-1) | `board.h` |
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| On-board RJ45 | GEM3 (INTID 95) | GEM0 (INTID 88) | `board.h` |
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| GEM IP | Cadence GEM3 | Cadence GEM3 | `gem.c` unchanged (just base addr / INTID) |
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| PHY | DP83867 RGMII | DP83867 RGMII (VMK180) | `phy_dp83867.c` unchanged |
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| MMU | EL3 ARMv8 | EL3 ARMv8 | `mmu.c` unchanged |
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| RNG | memuse entropy | memuse entropy | `entropy.c` unchanged |
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The reused 90% (`gem.c`, `phy_dp83867.c`, `mmu.c`, `entropy.c`, `main.c`, `target.ld`, `target_ddr.ld`) is identical to the ZCU102 port; only `board.h`, `uart.c`, `gic.c`, and the startup/Makefile breadcrumbs are Versal-specific.
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## Build
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```
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cd src/port/versal
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make CROSS_COMPILE=aarch64-none-elf- # OCM layout (default)
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make CROSS_COMPILE=aarch64-none-elf- LAYOUT=ddr # DDR layout for wolfBoot
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```
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Output: `app.elf`. Size info is printed at the end of the build.
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## JTAG boot (VMK180)
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The VMK180 must be in **JTAG boot mode** (SW1 mode pins = 0000) and
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power-cycled so the BootROM does not auto-boot Linux from SD/QSPI -- a
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booted Linux owns GEM0 and runtime-suspends its clock, which stalls the
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bare-metal driver. Then:
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```
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XSDB=/opt/Xilinx/<ver>/Vitis/bin/xsdb \
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BOOT_PDI=/path/to/vmk180_boot.pdi \
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./jtag/boot.sh
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```
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`jtag/boot.tcl` does `rst -system`, programs the boot PDI through the PMC
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(the PLM brings up DDR/clocks/MIO and de-isolates the A72), then resets
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A72 #0 (`-skip-activate-subsystem`, which lands at EL3) and loads
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`app.elf`. The PS console is on FT4232 **interface 1**
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(`VERSAL_VMK180_UART1`).
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## Hardware bring-up notes (what was Versal-specific)
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- **GEM RX is poll-driven.** The GICv3 CPU interface did not deliver the
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GEM SPI in this EL3 bring-up, so `eth_poll` polls `gem_isr` from the
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main loop to drain the RX ring (the IRQ path stays registered but
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dormant).
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- **GEM clock is owned by the PLM.** The CRL block is PMC/PLM-protected;
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a direct APU write to `CRL.GEM0_REF_CTRL` (`0xFF5E0118`, not the ZynqMP
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`+0x50`) stalls the bus. The PLM already configures the GEM clock, so
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`gem.c` does not touch it. The correct Versal offsets are documented in
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`board.h` for reference.
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- **Two DP83867 PHYs.** The VMK180 presents more than one PHY on the MDIO
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bus; `gem.c` scans all 32 addresses and prefers the one reporting copper
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link (the on-board RJ45 PHY answered at addr 1). Make sure the cable is
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in the **PS-GEM** RJ45, not the System Controller jack.
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- `SCR_EL3` IRQ/FIQ/EA routing is carried over from the ZCU102 fix and is
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harmless on the A72.
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## Files
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Identical layout to `src/port/zcu102/` plus `jtag/` (PDI-based JTAG
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loader). See that port's README for per-file responsibilities. The
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differences listed in the table above are the only substantive
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Versal-specific code.

‎src/port/versal/board.h‎

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/* board.h
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*
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* Copyright (C) 2026 wolfSSL Inc.
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*
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* This file is part of wolfIP TCP/IP stack.
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*
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* wolfIP is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 3 of the License, or
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* (at your option) any later version.
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*
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* wolfIP is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
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*
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* Xilinx Versal Gen 1 (VCxxxx / VMK180 board) PS register base
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* addresses and GIC SPI IDs. Values are derived from the Versal ACAP
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* Technical Reference Manual (AM011), the VMK180 board user guide,
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* and the published `versal.dtsi` device tree. No Xilinx BSP header
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* (xparameters.h) or xilstandalone code is referenced.
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*
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* UNTESTED ON HARDWARE -- code-only scaffold while the lab board is
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* unavailable. The structure mirrors src/port/zcu102/. Key
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* differences from ZynqMP are:
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* - Cortex-A72 (not A53), with PLM handoff at EL2
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* - GICv3 distributor + redistributor (no GICv2 legacy GICC)
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* - ARM PL011 UART (not Cadence)
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* - 2 GEMs (GEM0/GEM1) instead of 4; on-board RJ45 is GEM0 on VMK180
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*/
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#ifndef VERSAL_BOARD_H
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#define VERSAL_BOARD_H
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#include <stdint.h>
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/* ---------------------------------------------------------------------
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* Memory map (Versal PS)
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* ------------------------------------------------------------------- */
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#define DDR_BASE 0x00000000UL
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#define DDR_SIZE 0x80000000UL /* 2 GB lower bank */
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/* OCM on Versal lives at 0xFFFC0000 (256 KB). Same as ZynqMP. */
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#define OCM_BASE 0xFFFC0000UL
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#define OCM_SIZE 0x00040000UL
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/* ---------------------------------------------------------------------
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* PS peripherals
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* ------------------------------------------------------------------- */
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#define UART0_BASE 0xFF000000UL /* PL011 */
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#define UART1_BASE 0xFF010000UL /* PL011 */
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#define GEM0_BASE 0xFF0C0000UL /* on-board GEM (VMK180) */
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#define GEM1_BASE 0xFF0D0000UL
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#define CRL_APB_BASE 0xFF5E0000UL /* LPD clock & reset */
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#define IOU_SLCR_BASE 0xFF180000UL
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/* GICv3: distributor + redistributor */
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#define GICD_BASE 0xF9000000UL
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#define GICR_BASE 0xF9080000UL /* per-CPU redistributors */
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/* ---------------------------------------------------------------------
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* GIC SPI numbers as GIC INTIDs (ARM GIC numbering: SPI N -> INTID 32+N).
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* Versal versal.dtsi:
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* GEM0: GIC_SPI 56 -> INTID 88
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* GEM1: GIC_SPI 58 -> INTID 90
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* ------------------------------------------------------------------- */
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#define IRQ_GEM0 (32 + 56) /* GIC_SPI 56 -> INTID 88,
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* on-board VMK180 RJ45 */
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#define IRQ_GEM1 (32 + 58) /* GIC_SPI 58 -> INTID 90 */
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/* ---------------------------------------------------------------------
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* CRL clock and reset registers (LPD). Versal's CRL register map is NOT
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* the same as ZynqMP: the GEM clock/reset offsets differ. Verified
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* against the Versal PSM firmware crl.h (Vitis embeddedsw):
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* CRL.GEM0_REF_CTRL = CRL + 0x118 (CLKACT bit 25, DIVISOR0 [13:8],
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* SRCSEL [2:0])
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* CRL.RST_GEM0 = CRL + 0x308 (RESET bit 0)
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* ------------------------------------------------------------------- */
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#define CRL_APB_GEM0_REF_CTRL (CRL_APB_BASE + 0x118) /* Versal CRL.GEM0_REF_CTRL */
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#define CRL_GEM0_RST (CRL_APB_BASE + 0x308) /* Versal CRL.RST_GEM0 */
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#define CRL_GEM0_REF_CTRL_CLKACT (1u << 25)
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#define CRL_RST_GEM0_RESET (1u << 0)
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/* ---------------------------------------------------------------------
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* PL011 UART0 - on-board USB-UART on VMK180
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* ------------------------------------------------------------------- */
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#define UART_BAUD 115200
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/* MAC address for eth0. Locally-administered, even first octet. */
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#ifndef WOLFIP_MAC_0
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#define WOLFIP_MAC_0 0x02
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#endif
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#ifndef WOLFIP_MAC_1
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#define WOLFIP_MAC_1 0x00
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#endif
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#ifndef WOLFIP_MAC_2
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#define WOLFIP_MAC_2 0x5A
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#endif
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#ifndef WOLFIP_MAC_3
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#define WOLFIP_MAC_3 0x11
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#endif
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#ifndef WOLFIP_MAC_4
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#define WOLFIP_MAC_4 0x22
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#endif
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#ifndef WOLFIP_MAC_5
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#define WOLFIP_MAC_5 0x33
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#endif
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#endif /* VERSAL_BOARD_H */

‎src/port/versal/config.h‎

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/* config.h
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*
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* Copyright (C) 2026 wolfSSL Inc.
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*
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* This file is part of wolfIP TCP/IP stack.
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*
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* wolfIP is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 3 of the License, or
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* (at your option) any later version.
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*
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* wolfIP is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
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*
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* wolfIP configuration for Xilinx ZCU102 (UltraScale+ MPSoC, A53-0 EL3
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* bare-metal). UDP-only profile aimed at deterministic DAL-C use.
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*/
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#ifndef WOLF_CONFIG_H
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#define WOLF_CONFIG_H
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#ifndef CONFIG_IPFILTER
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#define CONFIG_IPFILTER 0
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#endif
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#define ETHERNET
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#define LINK_MTU 1536
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/* UDP-only profile in intent: the application does not call
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* wolfIP_sock_socket() with IPSTACK_SOCK_STREAM. MAX_TCPSOCKETS is set
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* to a small non-zero value only because core wolfIP currently sizes
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* its timer heap via MAX_TIMERS = MAX_TCPSOCKETS * 3, and DHCP / ARP
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* aging need timers. With MAX_TCPSOCKETS=0 the timer-heap insert path
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* is permanently full and DHCP cannot schedule its retransmit timer.
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* A core wolfIP follow-up should decouple MAX_TIMERS from
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* MAX_TCPSOCKETS so DAL-C builds can truly opt TCP code out at
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* compile time. */
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#define MAX_TCPSOCKETS 2
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#define MAX_UDPSOCKETS 4
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#define MAX_ICMPSOCKETS 1
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#define RXBUF_SIZE (LINK_MTU * 4)
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#define TXBUF_SIZE (LINK_MTU * 4)
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#define MAX_NEIGHBORS 16
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#ifndef WOLFIP_MAX_INTERFACES
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#define WOLFIP_MAX_INTERFACES 1
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#endif
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#ifndef WOLFIP_ENABLE_FORWARDING
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#define WOLFIP_ENABLE_FORWARDING 0
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#endif
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#ifndef WOLFIP_ENABLE_LOOPBACK
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#define WOLFIP_ENABLE_LOOPBACK 0
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#endif
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#ifndef WOLFIP_ENABLE_DHCP
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#define WOLFIP_ENABLE_DHCP 1
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#endif
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/* Static IP fallback (used if DHCP is disabled or times out). */
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#define WOLFIP_IP "192.168.1.100"
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#define WOLFIP_NETMASK "255.255.255.0"
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#define WOLFIP_GW "192.168.1.1"
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#define WOLFIP_STATIC_DNS_IP "8.8.8.8"
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#if WOLFIP_ENABLE_DHCP
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#define DHCP
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#define DHCP_DISCOVER_RETRIES 2
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#define DHCP_REQUEST_RETRIES 2
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#endif
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/* Hardware debug: define for verbose GEM / MDIO / DHCP logging. */
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/* #define DEBUG_HW */
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#endif /* WOLF_CONFIG_H */

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