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zynq7000: bare-metal wolfIP port for Zynq-7000 (Cortex-A9, ARMv7-A)
ZC702 bring-up: A9 in SVC mode, GIC-390, short-descriptor MMU, MPCore Global Timer (the A9 has no ARMv7 generic timer), UART1 console, Cadence GEM0 with a Marvell 88E1518 PHY driver (the ZC702 PHY, not DP83867), GEM clock/RGMII RX-clock via SLCR, poll-driven RX with the GEM IRQ masked, and non-cacheable OCM for DMA-coherent descriptors. FSBL-based xsdb JTAG loader. HW-tested on a ZC702: DHCP + ping + UDP echo.
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‎src/port/zynq7000/.gitignore‎

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*.o
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*.elf
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*.bin
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BOOT.BIN

‎src/port/zynq7000/Makefile‎

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# Xilinx Zynq-7000 (Cortex-A9, ARMv7-A 32-bit) wolfIP bare-metal port
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#
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# Build: make CROSS_COMPILE=arm-none-eabi-
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#
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# Toolchain: ARM GNU arm-none-eabi-gcc (tested with 13.2).
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#
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# UNTESTED ON HARDWARE -- structural scaffold mirroring src/port/zcu102/.
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CROSS_COMPILE ?= arm-none-eabi-
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CC := $(CROSS_COMPILE)gcc
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OBJCOPY := $(CROSS_COMPILE)objcopy
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SIZE := $(CROSS_COMPILE)size
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ROOT := ../../..
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# Cortex-A9, ARMv7-A 32-bit, no NEON in cert paths.
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CFLAGS := -mcpu=cortex-a9 -marm
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CFLAGS += -Os -ffreestanding -fno-builtin -fno-common
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CFLAGS += -fdata-sections -ffunction-sections
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CFLAGS += -g -Wall -Wextra -Werror -Wno-unused-parameter
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CFLAGS += -std=gnu99
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CFLAGS += -I. -I$(ROOT) -I$(ROOT)/src -I$(ROOT)/src/port
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CFLAGS += -DZYNQ7000 -DXILINX_ARMV7
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CFLAGS += $(CFLAGS_EXTRA)
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ASFLAGS := -mcpu=cortex-a9 -marm
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LDSCRIPT := target.ld
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LDFLAGS := -nostdlib -nostartfiles -T $(LDSCRIPT) -Wl,-gc-sections
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# Override newlib's memset/memcpy with bytewise variants in main.c
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# (the same "fast memset uses an instruction the bare-metal setup
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# does not tolerate" pattern we hit on the AArch64 port).
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LDFLAGS += -Wl,--wrap=memset -Wl,--wrap=memcpy
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LOCAL_C := main.c uart.c mmu.c gic.c gem.c phy_dp83867.c phy_marvell.c entropy.c
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LOCAL_S := startup.S
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LOCAL_OBJS := $(LOCAL_C:.c=.o) $(LOCAL_S:.S=.o)
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WOLFIP_OBJ := wolfip.o
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OBJS := $(LOCAL_OBJS) $(WOLFIP_OBJ)
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all: app.elf
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@echo "Built: app.elf"
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@$(SIZE) app.elf
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app.elf: $(OBJS) $(LDSCRIPT)
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$(CC) $(CFLAGS) $(OBJS) $(LDFLAGS) \
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-Wl,--start-group -lc -lgcc -Wl,--end-group -o $@
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$(WOLFIP_OBJ): $(ROOT)/src/wolfip.c
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$(CC) $(CFLAGS) -Wno-zero-length-bounds -Wno-type-limits -c $< -o $@
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%.o: %.c
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$(CC) $(CFLAGS) -c $< -o $@
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%.o: %.S
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$(CC) $(ASFLAGS) -c $< -o $@
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clean:
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rm -f $(OBJS) app.elf BOOT.BIN
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.PHONY: all clean help
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help:
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@echo "Zynq-7000 wolfIP build (scaffold, untested):"
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@echo " make - build app.elf"
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@echo " make clean - remove artifacts"
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@echo ""
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@echo "Override CROSS_COMPILE if your toolchain prefix differs."

‎src/port/zynq7000/README.md‎

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# wolfIP port: Xilinx Zynq-7000 (Cortex-A9, ARMv7-A 32-bit)
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**STATUS: brought up on a ZC702.** DHCP, ICMP ping and the UDP echo demo all work on real hardware (Cortex-A9, Marvell 88E1518 PHY). See "Hardware bring-up notes" below for the Zynq-7000-specific differences that mattered.
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## What this port is
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Bare-metal wolfIP port for the Xilinx Zynq-7000 family (Z-7020 etc., e.g. ZC702 / ZedBoard / MicroZed dev boards). Cortex-A9 in SVC mode, GCC bare-metal, no Xilinx Standalone BSP, no FreeRTOS. Targets the same deterministic UDP/IPv4 profile as the ZCU102 port.
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## What differs from ZCU102
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| Subsystem | ZCU102 (ZynqMP) | Zynq-7000 | Where it lives |
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|-----------|-----------------|-----------|----------------|
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| Architecture | ARMv8-A AArch64 | ARMv7-A 32-bit | toolchain prefix |
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| CPU core | Cortex-A53 | Cortex-A9 | `Makefile` (-mcpu) |
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| Bootloader handoff | FSBL -> EL3 | FSBL -> SVC | `startup.S` |
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| Toolchain | `aarch64-none-elf-gcc` | `arm-none-eabi-gcc` | `Makefile` |
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| Exception model | EL3 vectors | ARMv7 exception modes | `startup.S` rewritten |
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| MMU | 4-level long descriptor | 1-level short descriptor | `mmu.c` rewritten |
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| Cache ops | DC CVAC / DC IVAC | MCR p15 c7 (DCCMVAC/DCIMVAC) | `gem.c` |
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| Generic timer | `mrs cntpct_el0` | `mrrc p15, 0, ..., c14` | `timer.h`, `entropy.c` |
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| GIC | GIC-400 (GICv2) | GIC-390 (GICv2) | `gic.c` (same driver, different base) |
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| GIC base addrs | `0xF901xxxx` | `0xF8F0xxxx` | `board.h` |
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| UART | Cadence at 0xFF000000 | Cadence at 0xE0000000 | `board.h` (same driver) |
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| Clock + reset | CRL_APB at 0xFF5E0000 | SLCR at 0xF8000000 | `board.h` (gem.c clock helper needs rewrite) |
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| GEM count | 4 (GEM0-3) | 2 (GEM0-1) | `board.h` |
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| On-board RJ45 | GEM3 (INTID 95) | GEM0 (INTID 54) | `board.h` |
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| BD format | 8-byte (DMACR[30]=0) | 8-byte (no 64-bit option) | `gem.c` (unchanged) |
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## Build
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```
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cd src/port/zynq7000
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make CROSS_COMPILE=arm-none-eabi-
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```
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Output: `app.elf`.
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## JTAG boot (ZC702)
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The ZC702 boots its onboard JTAG over the Digilent USB module; set SW10
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to the on-board (USB) JTAG position and SW16 to JTAG boot mode, then:
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```
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XSDB=/opt/Xilinx/<ver>/Vitis/bin/xsdb \
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FSBL_ELF=/path/to/zynq_fsbl.elf \
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./jtag/boot.sh
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```
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`jtag/boot.tcl` runs the prebuilt FSBL (ps7_init brings up DDR/MIO/clocks/
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UART), remaps all four OCM banks high (`SLCR.OCM_CFG`) so the app can load
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at `0xFFFC0000`, then loads `app.elf` and starts it in SVC mode. The
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console is on **UART1** (the ZC702 USB-UART), not UART0. After a run the
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A9 must be power-cycled to be JTAG-loadable again.
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## Hardware bring-up notes (what was Zynq-7000-specific)
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These are the things that differed from the AArch64 ports and had to be
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fixed for the ZC702 to reach DHCP/ping/echo:
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- **No ARM generic timer.** The Cortex-A9 does not implement CNTPCT/CNTFRQ
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(CP15 c14); those encodings are UNDEFINED and trap. `timer.h` and
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`entropy.c` use the MPCore **Global Timer** at `0xF8F00200` (333 MHz)
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instead.
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- **Console is UART1.** The ZC702 routes the USB console to Cadence UART1
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(`0xE0001000`); `uart.c` trusts the FSBL's baud config rather than
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reprogramming the divisor (the UART_REF_CLK is not the ZynqMP value).
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- **Marvell 88E1518 PHY, not DP83867.** The ZC702 fits a Marvell PHY
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(OUI `0x0141`) at MDIO addr 7. `phy_marvell.c` handles its paged RGMII
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delay registers + autoneg; `gem.c` dispatches on the PHY ID.
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- **GEM clock via SLCR, write-protected.** `SLCR.GEM0_CLK_CTRL`
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(`0xF8000140`) has a different layout than ZynqMP's CRL_APB and is
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write-locked. `gem3_set_ref_clk` unlocks the SLCR (`0xDF0D`) and writes
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`0x00100801` for 125 MHz (1 Gbps). `SLCR.GEM0_RCLK_CTRL` (`0xF8000138`)
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must also be set to source the RGMII RX clock from the PHY, or the MAC
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receives nothing (matches Xilinx ps7_init).
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- **Poll-driven RX, GEM IRQ masked.** Unlike the Versal GICv3, the A9 GIC
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delivers the GEM SPI, and an enabled RX-complete interrupt storms the
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CPU. RX is polled from `eth_poll` and the GEM interrupt is left masked.
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- **Non-cacheable OCM for DMA.** The 8-byte GEM descriptors share 32-byte
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cache lines, so per-descriptor cache maintenance corrupts neighbours'
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OWN bits and stalls RX. The OCM section is mapped Normal non-cacheable
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(`mmu.c`) so the descriptor rings and buffers are DMA-coherent. (The
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PL310 L2 is also disabled as a belt-and-braces measure.) Note the A9
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L1 cache line is 32 bytes, not the 64 of the AArch64 cores.
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- `NWCFG_DWIDTH_64` (NWCFG bit 21) is never set: the A9 GEM AXI master
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path is 32-bit and the BDs stay 8 bytes.
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## Files
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Same layout as `src/port/zcu102/`, plus `phy_marvell.c` / `phy_marvell.h`
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(the ZC702 PHY) and `jtag/` (FSBL-based JTAG loader). See the ZCU102
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README for the shared per-file responsibilities.

‎src/port/zynq7000/board.h‎

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/* board.h
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*
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* Copyright (C) 2026 wolfSSL Inc.
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*
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* This file is part of wolfIP TCP/IP stack.
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*
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* wolfIP is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 3 of the License, or
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* (at your option) any later version.
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*
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* wolfIP is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
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*
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* Xilinx Zynq-7000 (Cortex-A9, ARMv7-A 32-bit) PS register base
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* addresses and GIC interrupt IDs. Derived from the Zynq-7000 TRM
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* (UG585). No Xilinx Standalone BSP header is required.
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*
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* UNTESTED ON HARDWARE -- code-only scaffold while the lab board is
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* unavailable. Mirrors src/port/zcu102/ structurally. Key differences:
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* - Cortex-A9 (not A53), ARMv7-A 32-bit (not AArch64)
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* - SLCR replaces ZynqMP's CRL_APB
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* - GIC-390 (GICv2) inside the SCU at different base addresses
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* - Cadence UART (same IP as ZynqMP; different base address)
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* - Cadence GEM (older revision; 32-bit BD format default)
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* - 2 GEMs (GEM0 / GEM1); on-board RJ45 is typically GEM0
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*/
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#ifndef ZYNQ7000_BOARD_H
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#define ZYNQ7000_BOARD_H
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#include <stdint.h>
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/* ---------------------------------------------------------------------
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* Memory map (Zynq-7000 PS)
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* ------------------------------------------------------------------- */
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#define DDR_BASE 0x00000000UL
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#define DDR_SIZE 0x40000000UL /* 1 GB typical, e.g. ZC702 */
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/* OCM is mappable to 0x00000000 (low) or 0xFFFC0000 (high). Most
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* bare-metal apps use the high mapping; FSBL configures the OCM
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* address filter via SLCR.OCM_CFG. We assume the high mapping. */
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#define OCM_BASE 0xFFFC0000UL
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#define OCM_SIZE 0x00040000UL /* 256 KB */
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/* ---------------------------------------------------------------------
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* PS peripherals
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* ------------------------------------------------------------------- */
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#define UART0_BASE 0xE0000000UL /* Cadence */
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#define UART1_BASE 0xE0001000UL
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#define GEM0_BASE 0xE000B000UL /* on-board RJ45 typical */
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#define GEM1_BASE 0xE000C000UL
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#define SLCR_BASE 0xF8000000UL /* clock + reset */
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/* GIC-390 (ARMv7 GICv2 compatible). Distributor + CPU IF are in the
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* SCU (Snoop Control Unit) memory region on Zynq-7000. */
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#define GICD_BASE 0xF8F01000UL
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#define GICC_BASE 0xF8F00100UL
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/* ---------------------------------------------------------------------
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* GIC interrupt IDs (raw GIC INTIDs, not GIC_SPI offsets).
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* Per Zynq-7000 TRM Table 7-3:
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* GEM0: INTID 54
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* GEM1: INTID 77
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* ------------------------------------------------------------------- */
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#define IRQ_GEM0 54
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#define IRQ_GEM1 77
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/* ---------------------------------------------------------------------
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* SLCR clock and reset registers
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* ------------------------------------------------------------------- */
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#define SLCR_LOCK (SLCR_BASE + 0x004)
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#define SLCR_UNLOCK (SLCR_BASE + 0x008)
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#define SLCR_GEM0_CLK_CTRL (SLCR_BASE + 0x140)
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#define SLCR_GEM0_RCLK_CTRL (SLCR_BASE + 0x138) /* RGMII RX clock src */
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#define SLCR_GEM1_CLK_CTRL (SLCR_BASE + 0x144)
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#define SLCR_GEM_RST_CTRL (SLCR_BASE + 0x214)
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#define SLCR_UNLOCK_KEY 0xDF0D /* per TRM */
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/* ---------------------------------------------------------------------
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* Cadence UART0 baud
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* ------------------------------------------------------------------- */
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#define UART_BAUD 115200
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/* MAC address for eth0. Locally-administered, even first octet. */
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#ifndef WOLFIP_MAC_0
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#define WOLFIP_MAC_0 0x02
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#endif
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#ifndef WOLFIP_MAC_1
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#define WOLFIP_MAC_1 0x00
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#endif
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#ifndef WOLFIP_MAC_2
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#define WOLFIP_MAC_2 0x5A
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#endif
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#ifndef WOLFIP_MAC_3
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#define WOLFIP_MAC_3 0x11
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#endif
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#ifndef WOLFIP_MAC_4
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#define WOLFIP_MAC_4 0x22
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#endif
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#ifndef WOLFIP_MAC_5
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#define WOLFIP_MAC_5 0x33
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#endif
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#endif /* ZYNQ7000_BOARD_H */

‎src/port/zynq7000/config.h‎

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/* config.h
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*
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* Copyright (C) 2026 wolfSSL Inc.
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*
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* This file is part of wolfIP TCP/IP stack.
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*
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* wolfIP is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 3 of the License, or
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* (at your option) any later version.
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*
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* wolfIP is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
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*
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* wolfIP configuration for Xilinx ZCU102 (UltraScale+ MPSoC, A53-0 EL3
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* bare-metal). UDP-only profile aimed at deterministic DAL-C use.
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*/
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#ifndef WOLF_CONFIG_H
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#define WOLF_CONFIG_H
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#ifndef CONFIG_IPFILTER
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#define CONFIG_IPFILTER 0
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#endif
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#define ETHERNET
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#define LINK_MTU 1536
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/* UDP-only profile in intent: the application does not call
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* wolfIP_sock_socket() with IPSTACK_SOCK_STREAM. MAX_TCPSOCKETS is set
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* to a small non-zero value only because core wolfIP currently sizes
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* its timer heap via MAX_TIMERS = MAX_TCPSOCKETS * 3, and DHCP / ARP
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* aging need timers. With MAX_TCPSOCKETS=0 the timer-heap insert path
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* is permanently full and DHCP cannot schedule its retransmit timer.
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* A core wolfIP follow-up should decouple MAX_TIMERS from
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* MAX_TCPSOCKETS so DAL-C builds can truly opt TCP code out at
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* compile time. */
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#define MAX_TCPSOCKETS 2
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#define MAX_UDPSOCKETS 4
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#define MAX_ICMPSOCKETS 1
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#define RXBUF_SIZE (LINK_MTU * 4)
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#define TXBUF_SIZE (LINK_MTU * 4)
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#define MAX_NEIGHBORS 16
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#ifndef WOLFIP_MAX_INTERFACES
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#define WOLFIP_MAX_INTERFACES 1
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#endif
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#ifndef WOLFIP_ENABLE_FORWARDING
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#define WOLFIP_ENABLE_FORWARDING 0
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#endif
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#ifndef WOLFIP_ENABLE_LOOPBACK
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#define WOLFIP_ENABLE_LOOPBACK 0
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#endif
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#ifndef WOLFIP_ENABLE_DHCP
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#define WOLFIP_ENABLE_DHCP 1
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#endif
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/* Static IP fallback (used if DHCP is disabled or times out). */
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#define WOLFIP_IP "192.168.1.100"
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#define WOLFIP_NETMASK "255.255.255.0"
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#define WOLFIP_GW "192.168.1.1"
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#define WOLFIP_STATIC_DNS_IP "8.8.8.8"
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#if WOLFIP_ENABLE_DHCP
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#define DHCP
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#define DHCP_DISCOVER_RETRIES 2
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#define DHCP_REQUEST_RETRIES 2
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#endif
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/* Hardware debug: define for verbose GEM / MDIO / DHCP logging. */
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/* #define DEBUG_HW */
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#endif /* WOLF_CONFIG_H */

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