Zynq-7000 port scaffold (Cortex-A9 ARMv7-A, GICv2, Cadence GEM) - untested

Author: dgarske

src/port/zynq7000/.gitignore

@@ -0,0 +1,4 @@
+*.o
+*.elf
+*.bin
+BOOT.BIN

src/port/zynq7000/Makefile

@@ -0,0 +1,69 @@
+# Xilinx Zynq-7000 (Cortex-A9, ARMv7-A 32-bit) wolfIP bare-metal port
+#
+# Build:    make CROSS_COMPILE=arm-none-eabi-
+#
+# Toolchain: ARM GNU arm-none-eabi-gcc (tested with 13.2).
+#
+# UNTESTED ON HARDWARE -- structural scaffold mirroring src/port/zcu102/.
+
+CROSS_COMPILE ?= arm-none-eabi-
+CC      := $(CROSS_COMPILE)gcc
+OBJCOPY := $(CROSS_COMPILE)objcopy
+SIZE    := $(CROSS_COMPILE)size
+
+ROOT := ../../..
+
+# Cortex-A9, ARMv7-A 32-bit, no NEON in cert paths.
+CFLAGS  := -mcpu=cortex-a9 -marm
+CFLAGS  += -Os -ffreestanding -fno-builtin -fno-common
+CFLAGS  += -fdata-sections -ffunction-sections
+CFLAGS  += -g -Wall -Wextra -Werror -Wno-unused-parameter
+CFLAGS  += -std=gnu99
+CFLAGS  += -I. -I$(ROOT) -I$(ROOT)/src -I$(ROOT)/src/port
+CFLAGS  += -DZYNQ7000 -DXILINX_ARMV7
+CFLAGS  += $(CFLAGS_EXTRA)
+
+ASFLAGS := -mcpu=cortex-a9 -marm
+
+LDSCRIPT := target.ld
+LDFLAGS  := -nostdlib -nostartfiles -T $(LDSCRIPT) -Wl,-gc-sections
+# Override newlib's memset/memcpy with bytewise variants in main.c
+# (the same "fast memset uses an instruction the bare-metal setup
+# does not tolerate" pattern we hit on the AArch64 port).
+LDFLAGS  += -Wl,--wrap=memset -Wl,--wrap=memcpy
+
+LOCAL_C := main.c uart.c mmu.c gic.c gem.c phy_dp83867.c entropy.c
+LOCAL_S := startup.S
+LOCAL_OBJS := $(LOCAL_C:.c=.o) $(LOCAL_S:.S=.o)
+
+WOLFIP_OBJ := wolfip.o
+OBJS := $(LOCAL_OBJS) $(WOLFIP_OBJ)
+
+all: app.elf
+	@echo "Built: app.elf"
+	@$(SIZE) app.elf
+
+app.elf: $(OBJS) $(LDSCRIPT)
+	$(CC) $(CFLAGS) $(OBJS) $(LDFLAGS) \
+	    -Wl,--start-group -lc -lgcc -Wl,--end-group -o $@
+
+$(WOLFIP_OBJ): $(ROOT)/src/wolfip.c
+	$(CC) $(CFLAGS) -Wno-zero-length-bounds -Wno-type-limits -c $< -o $@
+
+%.o: %.c
+	$(CC) $(CFLAGS) -c $< -o $@
+
+%.o: %.S
+	$(CC) $(ASFLAGS) -c $< -o $@
+
+clean:
+	rm -f $(OBJS) app.elf BOOT.BIN
+
+.PHONY: all clean help
+
+help:
+	@echo "Zynq-7000 wolfIP build (scaffold, untested):"
+	@echo "  make                         - build app.elf"
+	@echo "  make clean                   - remove artifacts"
+	@echo ""
+	@echo "Override CROSS_COMPILE if your toolchain prefix differs."

src/port/zynq7000/README.md

@@ -0,0 +1,56 @@
+# wolfIP port: Xilinx Zynq-7000 (Cortex-A9, ARMv7-A 32-bit)
+
+**STATUS: UNTESTED ON HARDWARE.** Structural scaffold mirroring `src/port/zcu102/`. The code compiles cleanly with `arm-none-eabi-gcc` but has not been brought up on a real Zynq-7000 board.
+
+## What this port is
+
+Bare-metal wolfIP port for the Xilinx Zynq-7000 family (Z-7020 etc., e.g. ZC702 / ZedBoard / MicroZed dev boards). Cortex-A9 in SVC mode, GCC bare-metal, no Xilinx Standalone BSP, no FreeRTOS. Targets the same deterministic UDP/IPv4 profile as the ZCU102 port.
+
+## What differs from ZCU102
+
+| Subsystem | ZCU102 (ZynqMP) | Zynq-7000 | Where it lives |
+|-----------|-----------------|-----------|----------------|
+| Architecture | ARMv8-A AArch64 | ARMv7-A 32-bit | toolchain prefix |
+| CPU core | Cortex-A53 | Cortex-A9 | `Makefile` (-mcpu) |
+| Bootloader handoff | FSBL -> EL3 | FSBL -> SVC | `startup.S` |
+| Toolchain | `aarch64-none-elf-gcc` | `arm-none-eabi-gcc` | `Makefile` |
+| Exception model | EL3 vectors | ARMv7 exception modes | `startup.S` rewritten |
+| MMU | 4-level long descriptor | 1-level short descriptor | `mmu.c` rewritten |
+| Cache ops | DC CVAC / DC IVAC | MCR p15 c7 (DCCMVAC/DCIMVAC) | `gem.c` |
+| Generic timer | `mrs cntpct_el0` | `mrrc p15, 0, ..., c14` | `timer.h`, `entropy.c` |
+| GIC | GIC-400 (GICv2) | GIC-390 (GICv2) | `gic.c` (same driver, different base) |
+| GIC base addrs | `0xF901xxxx` | `0xF8F0xxxx` | `board.h` |
+| UART | Cadence at 0xFF000000 | Cadence at 0xE0000000 | `board.h` (same driver) |
+| Clock + reset | CRL_APB at 0xFF5E0000 | SLCR at 0xF8000000 | `board.h` (gem.c clock helper needs rewrite) |
+| GEM count | 4 (GEM0-3) | 2 (GEM0-1) | `board.h` |
+| On-board RJ45 | GEM3 (INTID 95) | GEM0 (INTID 54) | `board.h` |
+| BD format | 8-byte (DMACR[30]=0) | 8-byte (no 64-bit option) | `gem.c` (unchanged) |
+
+## Build
+
+```
+cd src/port/zynq7000
+make CROSS_COMPILE=arm-none-eabi-
+```
+
+Output: `app.elf`.
+
+## Known unknowns (to validate on hardware)
+
+- `gem.c` still has `NWCFG_DWIDTH_64` available; it must not be set on Zynq-7000 (the A9 AXI master path is 32-bit; the older GEM revision does not implement that bit). Confirm `GEM_NWCFG` bit 21 stays clear during bring-up.
+- `gem.c` clock + reset code references `SLCR_GEM0_CLK_CTRL` / `SLCR_GEM_RST_CTRL`. The actual sequence will need an unlock (`SLCR_UNLOCK = 0xDF0D`) wrapper that does not exist in the AArch64 port.
+- DP83867 MDIO address on Zynq-7000 boards varies (ZedBoard uses a Marvell 88E1518; ZC702 / MicroZed differ). The shipped `phy_dp83867.c` only covers DP83867; confirm the actual on-board PHY before flashing.
+- `entropy.c` uses ARMv7 `MRRC p15, 1, ..., c14` for `cntvct_el0` (virtual counter). Cortex-A9 implements the generic timer differently from later cores; if `CNTFRQ` reads 0 the fallback (333 MHz) may be way off, causing `delay_us` to misbehave. Check `CNTFRQ` first thing during bring-up.
+- ARMv7 IRQ trampoline in `startup.S` uses `srsdb` + `rfeia` -- standard but assumes the IRQ-mode stack is reachable; an early IRQ before SVC stack init would fault. The current code disables IRQ until `irq_enable` is called after wolfIP/GEM init, which avoids the race.
+- `mmu.c` uses 1 MB sections (16 KB L1 table). All of DDR (1 GB) is mapped Normal-WB cacheable; the OCM high mapping at 0xFFFC0000 is in section 0xFFF mapped Normal-WB. PS peripherals are Device. The DMA carve-out logic from the AArch64 port is dropped because cache_clean/cache_inval handles coherency; reintroduce if the GEM exhibits coherency issues.
+
+## What was reused unchanged from ZCU102
+
+- `gem.c` core logic (BD ring, ISR, eth_send, eth_poll, MDIO) -- only the cache ops were rewritten for ARMv7 CP15.
+- `phy_dp83867.c` -- the DP83867 driver is host-architecture-independent.
+- `main.c` -- mostly identical; the AArch64-specific `exception_report` was dropped, the DEBUG_GIC self-test was `#if 0`-ed pending ARMv7 equivalents.
+- `entropy.c` -- only the timer-read primitive was rewritten.
+
+## Files
+
+Same layout as `src/port/zcu102/`. See that port's README for per-file responsibilities.

src/port/zynq7000/board.h

@@ -0,0 +1,112 @@
+/* board.h
+ *
+ * Copyright (C) 2026 wolfSSL Inc.
+ *
+ * This file is part of wolfIP TCP/IP stack.
+ *
+ * wolfIP is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfIP is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
+ *
+ * Xilinx Zynq-7000 (Cortex-A9, ARMv7-A 32-bit) PS register base
+ * addresses and GIC interrupt IDs. Derived from the Zynq-7000 TRM
+ * (UG585). No Xilinx Standalone BSP header is required.
+ *
+ * UNTESTED ON HARDWARE -- code-only scaffold while the lab board is
+ * unavailable. Mirrors src/port/zcu102/ structurally. Key differences:
+ *   - Cortex-A9 (not A53), ARMv7-A 32-bit (not AArch64)
+ *   - SLCR replaces ZynqMP's CRL_APB
+ *   - GIC-390 (GICv2) inside the SCU at different base addresses
+ *   - Cadence UART (same IP as ZynqMP; different base address)
+ *   - Cadence GEM (older revision; 32-bit BD format default)
+ *   - 2 GEMs (GEM0 / GEM1); on-board RJ45 is typically GEM0
+ */
+#ifndef ZYNQ7000_BOARD_H
+#define ZYNQ7000_BOARD_H
+
+#include <stdint.h>
+
+/* ---------------------------------------------------------------------
+ * Memory map (Zynq-7000 PS)
+ * ------------------------------------------------------------------- */
+#define DDR_BASE                0x00000000UL
+#define DDR_SIZE                0x40000000UL   /* 1 GB typical, e.g. ZC702 */
+
+/* OCM is mappable to 0x00000000 (low) or 0xFFFC0000 (high). Most
+ * bare-metal apps use the high mapping; FSBL configures the OCM
+ * address filter via SLCR.OCM_CFG. We assume the high mapping. */
+#define OCM_BASE                0xFFFC0000UL
+#define OCM_SIZE                0x00040000UL   /* 256 KB */
+
+/* ---------------------------------------------------------------------
+ * PS peripherals
+ * ------------------------------------------------------------------- */
+#define UART0_BASE              0xE0000000UL   /* Cadence */
+#define UART1_BASE              0xE0001000UL
+
+#define GEM0_BASE               0xE000B000UL   /* on-board RJ45 typical */
+#define GEM1_BASE               0xE000C000UL
+
+#define SLCR_BASE               0xF8000000UL   /* clock + reset */
+
+/* GIC-390 (ARMv7 GICv2 compatible). Distributor + CPU IF are in the
+ * SCU (Snoop Control Unit) memory region on Zynq-7000. */
+#define GICD_BASE               0xF8F01000UL
+#define GICC_BASE               0xF8F00100UL
+
+/* ---------------------------------------------------------------------
+ * GIC interrupt IDs (raw GIC INTIDs, not GIC_SPI offsets).
+ * Per Zynq-7000 TRM Table 7-3:
+ *   GEM0: INTID 54
+ *   GEM1: INTID 77
+ * ------------------------------------------------------------------- */
+#define IRQ_GEM0                54
+#define IRQ_GEM1                77
+
+/* ---------------------------------------------------------------------
+ * SLCR clock and reset registers
+ * ------------------------------------------------------------------- */
+#define SLCR_LOCK               (SLCR_BASE + 0x004)
+#define SLCR_UNLOCK             (SLCR_BASE + 0x008)
+#define SLCR_GEM0_CLK_CTRL      (SLCR_BASE + 0x140)
+#define SLCR_GEM1_CLK_CTRL      (SLCR_BASE + 0x144)
+#define SLCR_GEM_RST_CTRL       (SLCR_BASE + 0x214)
+
+#define SLCR_UNLOCK_KEY         0xDF0D     /* per TRM */
+
+/* ---------------------------------------------------------------------
+ * Cadence UART0 baud
+ * ------------------------------------------------------------------- */
+#define UART_BAUD               115200
+
+/* MAC address for eth0. Locally-administered, even first octet. */
+#ifndef WOLFIP_MAC_0
+#define WOLFIP_MAC_0            0x02
+#endif
+#ifndef WOLFIP_MAC_1
+#define WOLFIP_MAC_1            0x00
+#endif
+#ifndef WOLFIP_MAC_2
+#define WOLFIP_MAC_2            0x5A
+#endif
+#ifndef WOLFIP_MAC_3
+#define WOLFIP_MAC_3            0x11
+#endif
+#ifndef WOLFIP_MAC_4
+#define WOLFIP_MAC_4            0x22
+#endif
+#ifndef WOLFIP_MAC_5
+#define WOLFIP_MAC_5            0x33
+#endif
+
+#endif /* ZYNQ7000_BOARD_H */

src/port/zynq7000/config.h

@@ -0,0 +1,82 @@
+/* config.h
+ *
+ * Copyright (C) 2026 wolfSSL Inc.
+ *
+ * This file is part of wolfIP TCP/IP stack.
+ *
+ * wolfIP is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfIP is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
+ *
+ * wolfIP configuration for Xilinx ZCU102 (UltraScale+ MPSoC, A53-0 EL3
+ * bare-metal). UDP-only profile aimed at deterministic DAL-C use.
+ */
+#ifndef WOLF_CONFIG_H
+#define WOLF_CONFIG_H
+
+#ifndef CONFIG_IPFILTER
+#define CONFIG_IPFILTER         0
+#endif
+
+#define ETHERNET
+#define LINK_MTU                1536
+
+/* UDP-only profile in intent: the application does not call
+ * wolfIP_sock_socket() with IPSTACK_SOCK_STREAM. MAX_TCPSOCKETS is set
+ * to a small non-zero value only because core wolfIP currently sizes
+ * its timer heap via MAX_TIMERS = MAX_TCPSOCKETS * 3, and DHCP / ARP
+ * aging need timers. With MAX_TCPSOCKETS=0 the timer-heap insert path
+ * is permanently full and DHCP cannot schedule its retransmit timer.
+ * A core wolfIP follow-up should decouple MAX_TIMERS from
+ * MAX_TCPSOCKETS so DAL-C builds can truly opt TCP code out at
+ * compile time. */
+#define MAX_TCPSOCKETS          2
+#define MAX_UDPSOCKETS          4
+#define MAX_ICMPSOCKETS         1
+#define RXBUF_SIZE              (LINK_MTU * 4)
+#define TXBUF_SIZE              (LINK_MTU * 4)
+
+#define MAX_NEIGHBORS           16
+
+#ifndef WOLFIP_MAX_INTERFACES
+#define WOLFIP_MAX_INTERFACES   1
+#endif
+
+#ifndef WOLFIP_ENABLE_FORWARDING
+#define WOLFIP_ENABLE_FORWARDING 0
+#endif
+
+#ifndef WOLFIP_ENABLE_LOOPBACK
+#define WOLFIP_ENABLE_LOOPBACK  0
+#endif
+
+#ifndef WOLFIP_ENABLE_DHCP
+#define WOLFIP_ENABLE_DHCP      1
+#endif
+
+/* Static IP fallback (used if DHCP is disabled or times out). */
+#define WOLFIP_IP               "192.168.1.100"
+#define WOLFIP_NETMASK          "255.255.255.0"
+#define WOLFIP_GW               "192.168.1.1"
+#define WOLFIP_STATIC_DNS_IP    "8.8.8.8"
+
+#if WOLFIP_ENABLE_DHCP
+#define DHCP
+#define DHCP_DISCOVER_RETRIES 2
+#define DHCP_REQUEST_RETRIES  2
+#endif
+
+/* Hardware debug: define for verbose GEM / MDIO / DHCP logging. */
+/* #define DEBUG_HW */
+
+#endif /* WOLF_CONFIG_H */