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Add bare-metal wolfIP ports for UltraScale+ MPSoC (ZCU102), Versal VMK180 and Zynq-7000 (ZC702)
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‎src/port/amd/README.md‎

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# wolfIP AMD/Xilinx bare-metal ports
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Bare-metal wolfIP ports for AMD/Xilinx PS-GEM SoCs, sharing one tree:
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- **ZCU102** - ZynqMP, Cortex-A53, AArch64, EL3
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- **Versal Gen 1 / VMK180** - Cortex-A72, AArch64, EL3
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- **Zynq-7000 / ZC702** - Cortex-A9, ARMv7-A, SVC
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All three are brought up on real hardware (DHCP, ICMP ping, UDP echo).
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## Layout
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Shared code lives once; each board's Makefile selects which components to
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compile (build-selected files, not `#ifdef` forks).
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```
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common/ arch- and SoC-independent
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app.c app.h shared UDP-echo + DHCP demo (board hooks: board.c)
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gem_core.c gem.h shared Cadence GEM core (init, MDIO, polled TX, diag)
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gem_regs.h gem_port.h GEM register map / internal hook interface
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uart_util.c shared UART helpers (puts/puthex/putdec/putip4)
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entropy.c memuse-pattern RNG (counter via arch_counter64)
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wolfip_config.h shared wolfIP profile (board config.h includes it)
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gic.h uart.h mmu.h driver API headers
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arch/aarch64/ cache.h timer.h mmu_aarch64.c startup_aarch64.S exception_aarch64.c
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arch/armv7/ cache.h timer.h mmu_armv7.c startup_armv7.S
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ip/ per-IP-block drivers (build-selected)
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uart_cadence.c uart_pl011.c UART
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gic_gicv2.c gic_gicv3.c GIC
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gem_swq.c gem_rx_swq_poll.c gem_rx_poll.c RX delivery model (all boards poll)
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gem_rx_irq.c reference IRQ-driven RX (not built; see file)
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phy_dp83867.c phy_marvell.c PHY drivers
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phy_dispatch_dp83867.c phy_dispatch_multi.c PHY vendor dispatch
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boards/<board>/ the build root for each board (keeps app.elf + JTAG in place)
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board.h board.c board_gem.c config.h Makefile target*.ld jtag/ [bootgen/]
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```
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## Component selection per board
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| Component | ZCU102 | Versal | Zynq-7000 |
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|-----------|--------|--------|-----------|
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| arch | aarch64 | aarch64 | armv7 |
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| UART | cadence | pl011 | cadence |
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| GIC | gicv2 | gicv3 | gicv2 |
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| GEM RX | gem_rx_swq_poll + gem_swq | gem_rx_swq_poll + gem_swq | gem_rx_poll |
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| PHY | dp83867 | dp83867 | dp83867 + marvell (multi) |
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| GEM inst | GEM3 | GEM0 | GEM0 |
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## Build
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```
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cd boards/zcu102 && make CROSS_COMPILE=aarch64-none-elf-
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cd boards/versal && make CROSS_COMPILE=aarch64-none-elf-
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cd boards/zynq7000 && make CROSS_COMPILE=arm-none-eabi-
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```
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Output is `app.elf` in the board directory. See each board's `README.md`
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for the JTAG / BOOT.BIN flow and bring-up notes.
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## Throughput test (SPEED_TEST)
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The default build runs the UDP echo + DHCP demo. Building with
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`CFLAGS_EXTRA=-DSPEED_TEST` instead brings up a TCP throughput server on
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**port 9** (a discard/chargen-style sink + source, in the spirit of iperf but
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without iperf3's JSON control channel, which is impractical on bare metal). On
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each accepted connection the board sinks everything the host sends (RX) and, in
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the same window, sources chargen data whenever the socket is writable (TX); on
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close it prints the byte totals and an average rate over the UART:
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```
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cd boards/zcu102 && make CROSS_COMPILE=aarch64-none-elf- CFLAGS_EXTRA=-DSPEED_TEST
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```
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Measure from a host on the same subnet as the board (replace `<ip>` with the
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leased address printed at DHCP bind):
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```
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# RX (host -> board): how fast the board sinks
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dd if=/dev/zero bs=1460 count=20000 | nc -q1 <ip> 9
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# TX (board -> host): how fast the board sources
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nc <ip> 9 </dev/null | pv -r >/dev/null
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```
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The board's own `SPEED done ... RX/TX bytes (~B/s)` UART line is the
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authoritative figure (it times the connection with the hardware clock). Note
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the RX and TX counters cover the same connection window, so during the RX run
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the board is also back-sourcing; the printed RX B/s is the host->board goodput
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under that concurrent load. iperf3 host-to-host on the same link is a useful
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*link* reference, but the board is not an iperf3 endpoint.
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The `SPEED_TEST` build also widens the TCP window (`RXBUF_SIZE`/`TXBUF_SIZE` to
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`LINK_MTU * 6` in `config.h`) and trims the UDP socket count to keep the larger
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per-socket buffers inside the 256 KB OCM budget.
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### Results
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Single Cortex core, 1 Gbps RGMII link, MTU 1500, host on the same switch.
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RX is the board's UART `~B/s` line (host -> board); TX is host-measured
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(board -> host). Bytes x8 for Mbps.
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| Board (SoC, core) | Layout / boot | RX Mbps | TX Mbps |
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|------------------------------|-----------------|--------:|--------:|
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| VMK180 (Versal, A72 @ EL3) | DDR (JTAG) | ~300 | ~334 |
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| ZCU102 (ZynqMP, A53 @ EL3) | DDR (SD boot) | ~126 | ~194 |
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| ZC702 (Zynq-7000, A9 @ SVC) | OCM (JTAG) | ~22 | ~19 |
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| ZCU102 (ZynqMP, A53 @ EL3) | OCM (JTAG) | ~10 | ~9 |
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The single dominant factor is the **memory layout**: the OCM layout runs *all*
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code (and the rings) from Normal non-cacheable OCM, so every instruction fetch
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and frame copy is uncached. The DDR layout keeps code+data in cacheable DDR and
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maps only the GEM DMA region non-cacheable - ~13-30x faster, as the two ZCU102
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rows show directly (same SoC/core, OCM ~10/9 vs DDR ~126/194 Mbps). The faster
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A72 (Versal) reaches ~300/334 on DDR.
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How each DDR number was loaded: Versal's PLM trains DDR from a boot PDI, so the
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DDR app loads cleanly over JTAG. On ZynqMP, JTAG writes into DDR after a bare
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`psu_init` are unreliable (the load goes through the A53 with a cache flush and
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either errors or lands corrupt - DDR itself is fine, a direct DAP memtest passes),
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so the ZCU102 DDR figure is from an **SD boot**: `FSBL_ELF=.../zynqmp_fsbl.elf
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make bootbin` produces a DDR-layout `BOOT.BIN` that the FSBL trains DDR for and
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DMA-loads (no JTAG memory writes). Copy it to the SD card's FAT boot partition
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and set SW6 = SD. The same applies to ZC702 (its OCM-only port has no DDR layout
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yet; a DDR profile is future work).
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What it took to get here:
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1. **NC-map the DMA rings in the DDR layout (correctness, not just speed).**
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The DDR layout had mapped the GEM BD rings cacheable with per-BD
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`cache_clean`. Because the 8-byte BDs share 64-byte cache lines, cleaning one
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BD wrote stale neighbours back over MAC-set OWN bits and wedged the RX ring
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under sustained (TCP-rate) load - the UDP-only profile never had two BDs live
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in a line at once. The DMA region is now Normal-NC in both layouts, with
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`.dma_buffers` in its own 2 MB block so `.text` stays cacheable.
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2. **Main-loop poll cadence.** The original loop called `wolfIP_poll()` then
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`delay_ms(1)`, capping the stack at ~1 poll/ms (~12 Mbps) and feeding wolfIP
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a `tick++` counter that only approximated real milliseconds. It now
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busy-polls with a real-millisecond clock from the hardware timer
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(`timer_now()/timer_freq()`), which also de-skews every DHCP/TCP/ARP timeout.
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3. **Drain RX fully, bounded TX per event.** Reading one chunk per READABLE
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left the advertised TCP window stuck (~2 KB) and deadlocked; the SPEED server
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now drains the rx buffer each event and does a bounded tx fill.
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4. **Word-wise `memcpy`/`memset`.** Frame-staging copies are 8 bytes at a time
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(bytewise tail), which matters for the non-cacheable DMA buffers.
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Notes / remaining levers: ZCU102 uses the same poll-driven RX as the other two
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boards - its original IRQ-driven RX storms the CPU under sustained RX load.
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A DDR/BOOT.BIN profile for the OCM boards (cached code) and draining more than
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one frame per poll are the next levers.

‎src/port/amd/arch/aarch64/cache.h‎

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/* cache.h
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*
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* Copyright (C) 2026 wolfSSL Inc.
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*
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* This file is part of wolfIP TCP/IP stack.
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*
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* AArch64 (Cortex-A53/A72) cache maintenance for GEM DMA coherency. The
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* cache line is 64 bytes. With D-cache enabled and BD/buffers in normal
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* cacheable memory, CPU writes may sit in L1 and not be visible to the
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* MAC's DMA path. cache_clean() writes back dirty lines before DMA
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* reads; cache_inval() invalidates lines so CPU reads pull fresh
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* DMA-written data.
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*/
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#ifndef AMD_CACHE_H
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#define AMD_CACHE_H
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#include <stdint.h>
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#define CACHE_LINE 64u
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static inline void cache_clean(const void *p, uint32_t sz)
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{
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uintptr_t start = (uintptr_t)p & ~(CACHE_LINE - 1u);
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uintptr_t end = ((uintptr_t)p + sz + CACHE_LINE - 1u) & ~(CACHE_LINE - 1u);
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uintptr_t a;
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for (a = start; a < end; a += CACHE_LINE)
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__asm__ volatile ("dc cvac, %0" :: "r"(a) : "memory");
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__asm__ volatile ("dsb sy" ::: "memory");
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}
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static inline void cache_inval(const void *p, uint32_t sz)
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{
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uintptr_t start = (uintptr_t)p & ~(CACHE_LINE - 1u);
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uintptr_t end = ((uintptr_t)p + sz + CACHE_LINE - 1u) & ~(CACHE_LINE - 1u);
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uintptr_t a;
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for (a = start; a < end; a += CACHE_LINE)
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__asm__ volatile ("dc ivac, %0" :: "r"(a) : "memory");
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__asm__ volatile ("dsb sy" ::: "memory");
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}
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#endif /* AMD_CACHE_H */

‎src/port/amd/arch/aarch64/exception_aarch64.c‎

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/* exception_aarch64.c
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*
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* Copyright (C) 2026 wolfSSL Inc.
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*
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* This file is part of wolfIP TCP/IP stack.
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*
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* wolfIP is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 3 of the License, or
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* (at your option) any later version.
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*
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* wolfIP is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
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*
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* AArch64 EL3 fault reporters, called from the startup.S vector
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* trampolines on a synchronous exception or SError/FIQ. ARMv7 ports
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* just hang on faults (no C reporter), so this file is AArch64-only.
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*/
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#include <stdint.h>
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#include "uart.h"
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/* Called from startup.S vector trampoline on synchronous/SError fault. */
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void exception_report(uint64_t esr, uint64_t elr, uint64_t far, uint64_t spsr)
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{
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uart_puts("\n\n*** EL3 SYNC EXCEPTION ***\n");
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uart_puts(" ESR_EL3 : "); uart_puthex((uint32_t)(esr >> 32));
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uart_puthex((uint32_t)esr); uart_puts("\n");
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uart_puts(" EC = "); uart_puthex((uint32_t)((esr >> 26) & 0x3F));
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uart_puts(" (0x21=instr abort, 0x25=data abort, 0x24=alignment)\n");
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uart_puts(" ELR_EL3 : "); uart_puthex((uint32_t)(elr >> 32));
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uart_puthex((uint32_t)elr); uart_puts("\n");
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uart_puts(" FAR_EL3 : "); uart_puthex((uint32_t)(far >> 32));
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uart_puthex((uint32_t)far); uart_puts("\n");
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uart_puts(" SPSR_EL3: "); uart_puthex((uint32_t)spsr); uart_puts("\n");
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}
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void exception_report_serror(uint64_t esr, uint64_t elr, uint64_t far,
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uint64_t spsr, uint64_t kind)
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{
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(void)kind;
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uart_puts("\n\n*** EL3 SError / FIQ ***\n");
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uart_puts(" ESR_EL3 : "); uart_puthex((uint32_t)(esr >> 32));
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uart_puthex((uint32_t)esr); uart_puts("\n");
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uart_puts(" ELR_EL3 : "); uart_puthex((uint32_t)(elr >> 32));
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uart_puthex((uint32_t)elr); uart_puts("\n");
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uart_puts(" FAR_EL3 : "); uart_puthex((uint32_t)(far >> 32));
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uart_puthex((uint32_t)far); uart_puts("\n");
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uart_puts(" SPSR_EL3: "); uart_puthex((uint32_t)spsr); uart_puts("\n");
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}

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