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dgarskedgarske
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Adds new STM32 Bare support for Hash, SAES/AES and PKA
1 parent 460a871 commit b0ba9ce

9 files changed

Lines changed: 3234 additions & 90 deletions

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‎.wolfssl_known_macro_extras‎

Lines changed: 52 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,10 @@
1+
AES
2+
AES1
3+
AES_CR_CCFC
14
AES_GCM_GMULT_NCT
5+
AES_ICR_CCF
6+
AES_ISR_CCF
7+
AES_SR_CCF
28
AFX_RESOURCE_DLL
39
AFX_TARG_ENU
410
ALLOW_BINARY_MISMATCH_INTROSPECTION
@@ -269,7 +275,11 @@ HARDWARE_CACHE_COHERENCY
269275
HASH_AlgoMode_HASH
270276
HASH_AlgoMode_HMAC
271277
HASH_BYTE_SWAP
278+
HASH_CR_ALGO_1
279+
HASH_CR_DATATYPE_0
280+
HASH_CR_DATATYPE_1
272281
HASH_CR_LKEY
282+
HASH_CR_MODE
273283
HASH_DIGEST
274284
HASH_DataType_8b
275285
HASH_IMR_DCIE
@@ -491,14 +501,36 @@ OTHER_BOARD
491501
O_CLOEXEC
492502
PEER_INFO
493503
PERF_FLAG_FD_CLOEXEC
504+
PKA_CLRFR_OPERRFC
505+
PKA_CR_OPERRIE
494506
PKA_ECC_SCALAR_MUL_IN_B_COEFF
507+
PKA_SR_INITOK
508+
PKA_SR_OPERRF
495509
PLATFORMIO
496510
PLUTON_CRYPTO_ECC
497511
PRINT_SESSION_STATS
498512
PTHREAD_STACK_MIN
499513
QAT_ENABLE_HASH
500514
QAT_ENABLE_RNG
501515
QAT_USE_POLLING_CHECK
516+
RCC_AHB1ENR_PKAEN
517+
RCC_AHB2ENR1_AESEN
518+
RCC_AHB2ENR1_HASHEN
519+
RCC_AHB2ENR1_PKAEN
520+
RCC_AHB2ENR1_SAESEN
521+
RCC_AHB2ENR_AESEN
522+
RCC_AHB2ENR_HASHEN
523+
RCC_AHB2ENR_PKAEN
524+
RCC_AHB2ENR_SAESEN
525+
RCC_AHB3ENR_AESEN
526+
RCC_AHB3ENR_CRYPEN
527+
RCC_AHB3ENR_HASHEN
528+
RCC_AHB3ENR_PKAEN
529+
RCC_AHB3ENR_RNGEN
530+
RCC_AHB3ENR_SAESEN
531+
RCC_MP_AHB5ENSETR_CRYP1EN
532+
RCC_MP_AHB5ENSETR_HASH1EN
533+
RCC_MP_AHB5ENSETR_RNG1EN
502534
RC_NO_RNG
503535
REDIRECTION_IN3_KEYELMID
504536
REDIRECTION_IN3_KEYID
@@ -509,11 +541,18 @@ REDIRECTION_OUT2_KEYID
509541
RENESAS_T4_USE
510542
RHEL_MAJOR
511543
RHEL_RELEASE_CODE
544+
RNG_CAND_NIST_CR_VALUE
545+
RNG_CAND_NIST_HTCR_VALUE
546+
RNG_CAND_NIST_NSCR_VALUE
547+
RNG_CR_CONDRST
548+
RNG_SR_BUSY
512549
RTC_ALARMSUBSECONDMASK_ALL
513550
RTE_CMSIS_RTOS_RTX
514551
RTOS_MODULE_NET_AVAIL
515552
RTPLATFORM
516553
SAL_IOMMU_CODE
554+
SAES
555+
SAES_CR_EN
517556
SA_INTERRUPT
518557
SCEKEY_INSTALLED
519558
SHA256_MANY_REGISTERS
@@ -575,6 +614,7 @@ STM32WB55xx
575614
STM32WBA52xx
576615
STM32WL55xx
577616
STM32_AESGCM_PARTIAL
617+
STM32_AES_CLEAR_INST
578618
STM32_HW_CLOCK_AUTO
579619
STM32_NUTTX_RNG
580620
STSAFE_HOST_KEY_CIPHER
@@ -679,6 +719,11 @@ WC_SLHDSA_NO_ASM
679719
WC_SLHDSA_VERBOSE_DEBUG
680720
WC_SSIZE_TYPE
681721
WC_STRICT_SIG
722+
WC_STM32_PKA_DIAG
723+
WC_STM32_RNG_CED_DISABLE
724+
WC_STM32_RNG_DIAG
725+
WC_STM32_RNG_NO_NIST_INIT
726+
WC_STM32_SAES_DIAG
682727
WC_USE_PIE_FENCEPOSTS_FOR_FIPS
683728
WC_WANT_FLAG_DONT_USE_VECTOR_OPS
684729
WIFIESPAT
@@ -918,9 +963,14 @@ WOLFSSL_SP_ARM32_UDIV
918963
WOLFSSL_SP_FAST_NCT_EXPTMOD
919964
WOLFSSL_SP_INT_SQR_VOLATILE
920965
WOLFSSL_STACK_CHECK
966+
WOLFSSL_STM32C5
967+
WOLFSSL_STM32F3
921968
WOLFSSL_STM32F427_RNG
922-
WOLFSSL_STM32U5_DHUK
923-
WOLFSSL_STM32_RNG_NOLIB
969+
WOLFSSL_STM32U0
970+
WOLFSSL_STM32_AES_TYPEDEF_ALIAS
971+
WOLFSSL_STM32_BARE
972+
WOLFSSL_STM32_DHUK_UNWRAP
973+
WOLFSSL_STM32_USE_SAES
924974
WOLFSSL_STRONGEST_HASH_SIG
925975
WOLFSSL_STSAFE_TAKES_SLOT
926976
WOLFSSL_TELIT_M2MB

‎wolfcrypt/src/aes.c‎

Lines changed: 78 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -233,6 +233,16 @@ block cipher mechanism that uses n-bit binary string parameter key with 128-bits
233233
static WARN_UNUSED_RESULT int wc_AesEncrypt(
234234
Aes* aes, const byte* inBlock, byte* outBlock)
235235
{
236+
#ifdef WOLFSSL_STM32_BARE
237+
/* Bare-metal driver handles mutex, clock and key/IV internally. */
238+
#ifdef WOLFSSL_DHUK
239+
if (aes->devId == WOLFSSL_DHUK_WRAPPED_DEVID) {
240+
return wc_Stm32_Aes_DhukOp(aes, outBlock, inBlock,
241+
WC_AES_BLOCK_SIZE, 1 /* encrypt */);
242+
}
243+
#endif
244+
return wc_Stm32_Aes_Ecb(aes, outBlock, inBlock, WC_AES_BLOCK_SIZE, 1);
245+
#else
236246
int ret = 0;
237247
#ifdef WOLFSSL_STM32_CUBEMX
238248
CRYP_HandleTypeDef hcryp;
@@ -247,13 +257,13 @@ block cipher mechanism that uses n-bit binary string parameter key with 128-bits
247257
return ret;
248258
#endif
249259

250-
#ifdef WOLFSSL_STM32U5_DHUK
260+
#ifdef WOLFSSL_DHUK
251261
ret = wolfSSL_CryptHwMutexLock();
252262
if (ret != 0)
253263
return ret;
254264

255265
/* Handle making use of wrapped key */
256-
if (aes->devId == WOLFSSL_STM32U5_DHUK_WRAPPED_DEVID) {
266+
if (aes->devId == WOLFSSL_DHUK_WRAPPED_DEVID) {
257267
CRYP_ConfigTypeDef Config = {0};
258268

259269
ret = wc_Stm32_Aes_UnWrap(aes, &hcryp, (const byte*)aes->key,
@@ -373,6 +383,7 @@ block cipher mechanism that uses n-bit binary string parameter key with 128-bits
373383
wc_Stm32_Aes_Cleanup();
374384

375385
return ret;
386+
#endif /* !WOLFSSL_STM32_BARE */
376387
}
377388
#endif /* WOLFSSL_AES_DIRECT || HAVE_AESGCM || HAVE_AESCCM */
378389

@@ -381,6 +392,15 @@ block cipher mechanism that uses n-bit binary string parameter key with 128-bits
381392
static WARN_UNUSED_RESULT int wc_AesDecrypt(
382393
Aes* aes, const byte* inBlock, byte* outBlock)
383394
{
395+
#ifdef WOLFSSL_STM32_BARE
396+
#ifdef WOLFSSL_DHUK
397+
if (aes->devId == WOLFSSL_DHUK_WRAPPED_DEVID) {
398+
return wc_Stm32_Aes_DhukOp(aes, outBlock, inBlock,
399+
WC_AES_BLOCK_SIZE, 0 /* decrypt */);
400+
}
401+
#endif
402+
return wc_Stm32_Aes_Ecb(aes, outBlock, inBlock, WC_AES_BLOCK_SIZE, 0);
403+
#else
384404
int ret = 0;
385405
#ifdef WOLFSSL_STM32_CUBEMX
386406
CRYP_HandleTypeDef hcryp;
@@ -395,13 +415,13 @@ block cipher mechanism that uses n-bit binary string parameter key with 128-bits
395415
return ret;
396416
#endif
397417

398-
#ifdef WOLFSSL_STM32U5_DHUK
418+
#ifdef WOLFSSL_DHUK
399419
ret = wolfSSL_CryptHwMutexLock();
400420
if (ret != 0)
401421
return ret;
402422

403423
/* Handle making use of wrapped key */
404-
if (aes->devId == WOLFSSL_STM32U5_DHUK_WRAPPED_DEVID) {
424+
if (aes->devId == WOLFSSL_DHUK_WRAPPED_DEVID) {
405425
CRYP_ConfigTypeDef Config;
406426

407427
XMEMSET(&Config, 0, sizeof(Config));
@@ -527,6 +547,7 @@ block cipher mechanism that uses n-bit binary string parameter key with 128-bits
527547
wc_Stm32_Aes_Cleanup();
528548

529549
return ret;
550+
#endif /* !WOLFSSL_STM32_BARE */
530551
}
531552
#endif /* WOLFSSL_AES_DIRECT */
532553
#endif /* HAVE_AES_DECRYPT */
@@ -5663,7 +5684,34 @@ int wc_AesSetIV(Aes* aes, const byte* iv)
56635684
#ifdef HAVE_AES_CBC
56645685
#if defined(STM32_CRYPTO)
56655686

5666-
#ifdef WOLFSSL_STM32U5_DHUK
5687+
#ifdef WOLFSSL_STM32_BARE
5688+
int wc_AesCbcEncrypt(Aes* aes, byte* out, const byte* in, word32 sz)
5689+
{
5690+
#ifdef WOLFSSL_AES_CBC_LENGTH_CHECKS
5691+
if (sz % WC_AES_BLOCK_SIZE) {
5692+
return BAD_LENGTH_E;
5693+
}
5694+
#endif
5695+
if (sz == 0) {
5696+
return 0;
5697+
}
5698+
return wc_Stm32_Aes_Cbc(aes, out, in, sz, 1);
5699+
}
5700+
#ifdef HAVE_AES_DECRYPT
5701+
int wc_AesCbcDecrypt(Aes* aes, byte* out, const byte* in, word32 sz)
5702+
{
5703+
#ifdef WOLFSSL_AES_CBC_LENGTH_CHECKS
5704+
if (sz % WC_AES_BLOCK_SIZE) {
5705+
return BAD_LENGTH_E;
5706+
}
5707+
#endif
5708+
if (sz == 0) {
5709+
return 0;
5710+
}
5711+
return wc_Stm32_Aes_Cbc(aes, out, in, sz, 0);
5712+
}
5713+
#endif /* HAVE_AES_DECRYPT */
5714+
#elif defined(WOLFSSL_DHUK)
56675715
int wc_AesCbcEncrypt(Aes* aes, byte* out, const byte* in, word32 sz)
56685716
{
56695717
int ret = 0;
@@ -5683,7 +5731,7 @@ int wc_AesSetIV(Aes* aes, const byte* iv)
56835731
return ret;
56845732
}
56855733

5686-
if (aes->devId == WOLFSSL_STM32U5_DHUK_WRAPPED_DEVID) {
5734+
if (aes->devId == WOLFSSL_DHUK_WRAPPED_DEVID) {
56875735
CRYP_ConfigTypeDef Config;
56885736

56895737
XMEMSET(&Config, 0, sizeof(Config));
@@ -5749,7 +5797,7 @@ int wc_AesSetIV(Aes* aes, const byte* iv)
57495797
return ret;
57505798
}
57515799

5752-
if (aes->devId == WOLFSSL_STM32U5_DHUK_WRAPPED_DEVID) {
5800+
if (aes->devId == WOLFSSL_DHUK_WRAPPED_DEVID) {
57535801
CRYP_ConfigTypeDef Config;
57545802

57555803
XMEMSET(&Config, 0, sizeof(Config));
@@ -7046,6 +7094,11 @@ int wc_AesCbcEncrypt(Aes* aes, byte* out, const byte* in, word32 sz)
70467094

70477095
int wc_AesCtrEncryptBlock(Aes* aes, byte* out, const byte* in)
70487096
{
7097+
#ifdef WOLFSSL_STM32_BARE
7098+
/* CTR per-block transform: ECB-encrypt the counter (passed in
7099+
* 'in'); aes.c handles counter increment and XOR with plaintext. */
7100+
return wc_Stm32_Aes_Ecb(aes, out, in, WC_AES_BLOCK_SIZE, 1);
7101+
#else
70497102
int ret = 0;
70507103
#ifdef WOLFSSL_STM32_CUBEMX
70517104
CRYP_HandleTypeDef hcryp;
@@ -7156,6 +7209,7 @@ int wc_AesCbcEncrypt(Aes* aes, byte* out, const byte* in, word32 sz)
71567209
wolfSSL_CryptHwMutexUnLock();
71577210
wc_Stm32_Aes_Cleanup();
71587211
return ret;
7212+
#endif /* !WOLFSSL_STM32_BARE */
71597213
}
71607214

71617215

@@ -10246,6 +10300,7 @@ int wc_AesGcmEncrypt(Aes* aes, byte* out, const byte* in, word32 sz,
1024610300
authTag, authTagSz,
1024710301
authIn, authInSz);
1024810302
#endif
10303+
1024910304
#if defined(WOLFSSL_MICROCHIP_TA100) && defined(WOLFSSL_MICROCHIP_AESGCM)
1025010305
#ifndef TA_AES_GCM_MAX_DATA_SIZE
1025110306
#define TA_AES_GCM_MAX_DATA_SIZE 996u
@@ -10263,6 +10318,17 @@ int wc_AesGcmEncrypt(Aes* aes, byte* out, const byte* in, word32 sz,
1026310318
authIn, authInSz);
1026410319
}
1026510320
#endif
10321+
10322+
#if defined(WOLFSSL_STM32_BARE) && defined(STM32_CRYPTO)
10323+
ret = wc_Stm32_Aes_Gcm(aes, out, in, sz, iv, ivSz,
10324+
authTag, authTagSz,
10325+
authIn, authInSz, 1 /* enc */);
10326+
if (ret != WC_NO_ERR_TRACE(CRYPTOCB_UNAVAILABLE))
10327+
return ret;
10328+
/* fall through to SW GCM (still uses HW AES via wc_AesEncrypt) */
10329+
#endif /* WOLFSSL_STM32_BARE && STM32_CRYPTO */
10330+
10331+
1026610332
#ifdef STM32_CRYPTO_AES_GCM
1026710333
return wc_AesGcmEncrypt_STM32(
1026810334
aes, out, in, sz, iv, ivSz,
@@ -11007,6 +11073,10 @@ int wc_AesGcmDecrypt(Aes* aes, byte* out, const byte* in, word32 sz,
1100711073
}
1100811074
#endif
1100911075

11076+
/* BARE: GCM decrypt always uses SW path (with HW AES blocks via
11077+
* wc_AesEncrypt). Encrypt is HW-accelerated above; decrypt + tag
11078+
* verification stays in well-tested SW for now. */
11079+
1101011080
#ifdef STM32_CRYPTO_AES_GCM
1101111081
/* The STM standard peripheral library API's doesn't support partial blocks */
1101211082
return wc_AesGcmDecrypt_STM32(
@@ -13831,7 +13901,7 @@ int wc_AesInit(Aes* aes, void* heap, int devId)
1383113901

1383213902
aes->heap = heap;
1383313903

13834-
#if defined(WOLF_CRYPTO_CB) || defined(WOLFSSL_STM32U5_DHUK)
13904+
#if defined(WOLF_CRYPTO_CB) || defined(WOLFSSL_DHUK)
1383513905
aes->devId = devId;
1383613906
aes->devCtx = NULL;
1383713907
#else

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