Add RVV vector length

Author: AntoinePrv

include/xsimd/config/xsimd_cpu_features_riscv.hpp

@@ -12,6 +12,9 @@
 #ifndef XSIMD_CPU_FEATURES_RISCV_HPP
 #define XSIMD_CPU_FEATURES_RISCV_HPP
 
+#include <cstddef>
+#include <cstdint>
+
 #include "./xsimd_config.hpp"
 #include "./xsimd_getauxval.hpp"
 
@@ -24,16 +27,47 @@
 
 namespace xsimd
 {
+    namespace detail
+    {
+        using riscv_reg64_t = std::uint64_t;
+
+        /**
+         * Return the RVV vector length in bytes.
+         *
+         * This does not require to be compiles with SVE, which should not
+         * be done in a dynamic dispatch jump function.
+         *
+         * Safety: It is the user responsibility to first make sure that RVV is
+         * available.
+         */
+        inline riscv_reg64_t riscv_csrr_unsafe();
+    }
+
     class riscv_cpu_features : private linux_hwcap_backend_default
     {
     public:
         inline bool rvv() const noexcept;
+        inline std::size_t rvv_size_bytes() const noexcept;
     };
 
     /********************
      *  Implementation  *
      ********************/
 
+    namespace detail
+    {
+#if XSIMD_TARGET_RISCV && (defined(__GNUC__) || defined(__clang__))
+        __attribute__((target("arch=+v"))) inline riscv_reg64_t riscv_csrr_unsafe()
+        {
+            riscv_reg64_t vlenb;
+            __asm__ volatile("csrr %0, vlenb" : "=r"(vlenb));
+            return vlenb;
+        }
+#else
+        inline riscv_reg64_t riscv_csrr_unsafe() { return 0; }
+#endif
+    }
+
     inline bool riscv_cpu_features::rvv() const noexcept
     {
 #if XSIMD_TARGET_RISCV && XSIMD_HAVE_LINUX_GETAUXVAL
@@ -47,6 +81,15 @@ namespace xsimd
         return false;
 #endif
     }
+
+    inline std::size_t riscv_cpu_features::rvv_size_bytes() const noexcept
+    {
+        if (rvv())
+        {
+            return detail::riscv_csrr_unsafe();
+        }
+        return 0;
+    }
 }
 
 #endif

test/test_cpu_features.cpp

@@ -156,6 +156,13 @@ TEST_CASE("[cpu_features] arm features from environment")
     CHECK_ENV_FEATURE("XSIMD_TEST_CPU_ASSUME_I8MM", cpu.i8mm());
 }
 
+TEST_CASE("[cpu_features] risc-v implication chains")
+{
+    xsimd::riscv_cpu_features cpu;
+
+    CHECK_IMPLICATION(cpu.rvv(), cpu.rvv_size_bytes() >= 128);
+}
+
 TEST_CASE("[cpu_features] risc-v features from environment")
 {
     xsimd::riscv_cpu_features cpu;