Add SVE vector length

Author: AntoinePrv

include/xsimd/config/xsimd_cpu_features_arm.hpp

@@ -12,6 +12,9 @@
 #ifndef XSIMD_CPU_FEATURES_ARM_HPP
 #define XSIMD_CPU_FEATURES_ARM_HPP
 
+#include <cstddef>
+#include <cstdint>
+
 #include "./xsimd_config.hpp"
 #include "./xsimd_getauxval.hpp"
 
@@ -24,6 +27,24 @@
 
 namespace xsimd
 {
+
+    namespace detail
+    {
+        using arm_reg64_t = std::uint64_t;
+
+        /**
+         * Return the SVE vector length in bytes for the current thread.
+         *
+         * SVE vector length can be restricted
+         * Contrary to `svcntb` this does not require to be compiles with SVE, which
+         * should not be done in a dynamic dispatch jump function.
+         *
+         * Safety: It is the user responsibility to first make sure that SVE is
+         * available.
+         */
+        inline arm_reg64_t arm_rdvl_unsafe();
+    }
+
     /**
      * An opinionated CPU feature detection utility for ARM.
      *
@@ -40,13 +61,28 @@ namespace xsimd
         inline bool neon() const noexcept;
         inline bool neon64() const noexcept;
         inline bool sve() const noexcept;
+        inline std::size_t sve_size_bytes() const noexcept;
         inline bool i8mm() const noexcept;
     };
 
     /********************
      *  Implementation  *
      ********************/
 
+    namespace detail
+    {
+#if XSIMD_TARGET_ARM64 && (defined(__GNUC__) || defined(__clang__))
+        __attribute__((target("arch=armv8-a+sve"))) inline arm_reg64_t arm_rdvl_unsafe()
+        {
+            arm_reg64_t vl;
+            __asm__ volatile("rdvl %0, #1" : "=r"(vl));
+            return vl;
+        }
+#else
+        inline arm_reg64_t arm_rdvl_unsafe() { return 0; }
+#endif
+    }
+
     inline bool arm_cpu_features::neon() const noexcept
     {
 #if XSIMD_TARGET_ARM && !XSIMD_TARGET_ARM64 && XSIMD_HAVE_LINUX_GETAUXVAL
@@ -70,6 +106,15 @@ namespace xsimd
 #endif
     }
 
+    inline std::size_t arm_cpu_features::sve_size_bytes() const noexcept
+    {
+        if (sve())
+        {
+            return detail::arm_rdvl_unsafe();
+        }
+        return 0;
+    }
+
     inline bool arm_cpu_features::i8mm() const noexcept
     {
 #if XSIMD_TARGET_ARM64 && XSIMD_HAVE_LINUX_GETAUXVAL

test/test_cpu_features.cpp

@@ -142,6 +142,7 @@ TEST_CASE("[cpu_features] arm implication chains")
 
     CHECK_IMPLICATION(cpu.neon64(), cpu.neon());
     CHECK_IMPLICATION(cpu.sve(), cpu.neon64());
+    CHECK_IMPLICATION(cpu.sve(), cpu.sve_size_bytes() >= 128);
     CHECK_IMPLICATION(cpu.i8mm(), cpu.neon64());
 }