Document all xcr0 bits

Author: AntoinePrv

include/xsimd/config/xsimd_cpu_features_x86.hpp

@@ -56,7 +56,7 @@ namespace xsimd
         constexpr static x86_xcr0 safe_default() noexcept
         {
             reg_t low = {};
-            low = utils::set_bit<sse_bit>(low);
+            low = utils::set_bit<static_cast<reg_t>(bit::sse)>(low);
             return x86_xcr0(low);
         }
 
@@ -71,28 +71,52 @@ namespace xsimd
 
         constexpr bool sse_enabled() const noexcept
         {
-            return utils::bit_is_set<sse_bit>(m_low);
+            return bit_is_set<bit::sse>(m_low);
         }
 
         constexpr bool avx_enabled() const noexcept
         {
             // Check both SSE and AVX bits even though AVX must imply SSE
-            return utils::bit_is_set<sse_bit, avx_bit>(m_low);
+            return bit_is_set<bit::sse, bit::avx>(m_low);
         }
 
         constexpr bool avx512_enabled() const noexcept
         {
             // Check all SSE, AVX, and AVX512 bits even though AVX512 must
             // imply AVX and SSE
-            return utils::bit_is_set<sse_bit, avx_bit, avx512_bit>(m_low);
+            return bit_is_set<bit::sse, bit::avx, bit::zmm_hi256>(m_low);
         }
 
     private:
         using reg_t = detail::xcr0_reg_t;
 
-        static constexpr reg_t sse_bit = 1;
-        static constexpr reg_t avx_bit = 2;
-        static constexpr reg_t avx512_bit = 6;
+        enum class bit : reg_t
+        {
+            /** x87 FPU/MMX support (must be 1). */
+            x87 = 0,
+            /** XSAVE support for MXCSR and XMM registers. */
+            sse = 1,
+            /** AVX enabled and XSAVE support for upper halves of YMM registers. */
+            avx = 2,
+            /** MPX enabled and XSAVE support for BND0-BND3 registers. */
+            bndreg = 3,
+            /** MPX enabled and XSAVE support for BNDCFGU and BNDSTATUS registers. */
+            bndcsr = 4,
+            /** AVX-512 enabled and XSAVE support for opmask registers k0-k7. */
+            opmask = 5,
+            /** AVX-512 enabled and XSAVE support for upper halves of lower ZMM registers. */
+            zmm_hi256 = 6,
+            /** AVX-512 enabled and XSAVE support for upper ZMM registers. */
+            hi16_zmm = 7,
+            /** XSAVE support for PKRU register. */
+            pkru = 9,
+        };
+
+        template <bit... Bits>
+        static constexpr bool bit_is_set(reg_t value) noexcept
+        {
+            return utils::bit_is_set<static_cast<reg_t>(Bits)...>(value);
+        }
 
         /** Parse a XCR0 value into individual components. */
         constexpr explicit x86_xcr0(reg_t low) noexcept