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serge-sans-pailleserge-sans-paille
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Tentative support for avx2 extensions to 128 bit registers
1 parent 9748316 commit 3a61c90

5 files changed

Lines changed: 193 additions & 1 deletion

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‎.github/workflows/linux.yml‎

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@@ -17,6 +17,7 @@ jobs:
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- { compiler: 'gcc', version: '12', flags: 'force_no_instr_set' }
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- { compiler: 'gcc', version: '13', flags: 'enable_xtl_complex' }
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- { compiler: 'gcc', version: '14', flags: 'avx' }
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- { compiler: 'gcc', version: '14', flags: 'avx2' }
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- { compiler: 'gcc', version: '13', flags: 'avx512' }
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- { compiler: 'gcc', version: '10', flags: 'avx512' }
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- { compiler: 'gcc', version: '12', flags: 'i386' }
@@ -30,6 +31,7 @@ jobs:
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- { compiler: 'clang', version: '17', flags: 'sse3' }
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- { compiler: 'clang', version: '18', flags: 'avx512' }
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- { compiler: 'clang', version: '18', flags: 'avx_128' }
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- { compiler: 'clang', version: '18', flags: 'avx2_128' }
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steps:
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- name: Setup compiler
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if: ${{ matrix.sys.compiler == 'gcc' }}
@@ -80,6 +82,12 @@ jobs:
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if [[ '${{ matrix.sys.flags }}' == 'avx_128' ]]; then
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CMAKE_EXTRA_ARGS="$CMAKE_EXTRA_ARGS -DTARGET_ARCH=sandybridge -DXSIMD_DEFAULT_ARCH=avx_128"
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fi
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if [[ '${{ matrix.sys.flags }}' == 'avx2' ]]; then
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CMAKE_EXTRA_ARGS="$CMAKE_EXTRA_ARGS -DTARGET_ARCH=haswell"
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fi
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if [[ '${{ matrix.sys.flags }}' == 'avx2_128' ]]; then
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CMAKE_EXTRA_ARGS="$CMAKE_EXTRA_ARGS -DTARGET_ARCH=haswell -DXSIMD_DEFAULT_ARCH=avx2_128"
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fi
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if [[ '${{ matrix.sys.flags }}' == 'sse3' ]]; then
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CMAKE_EXTRA_ARGS="$CMAKE_EXTRA_ARGS -DTARGET_ARCH=nocona"
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fi

‎include/xsimd/arch/xsimd_avx2_128.hpp‎

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@@ -0,0 +1,170 @@
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/***************************************************************************
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* Copyright (c) Johan Mabille, Sylvain Corlay, Wolf Vollprecht and *
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* Martin Renou *
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* Copyright (c) QuantStack *
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* Copyright (c) Serge Guelton *
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* Copyright (c) Marco Barbone *
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* *
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* Distributed under the terms of the BSD 3-Clause License. *
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* *
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* The full license is in the file LICENSE, distributed with this software. *
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****************************************************************************/
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#ifndef XSIMD_AVX2_128_HPP
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#define XSIMD_AVX2_128_HPP
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#include <type_traits>
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#include "../types/xsimd_avx2_register.hpp"
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#include "../types/xsimd_batch_constant.hpp"
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namespace xsimd
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{
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namespace kernel
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{
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using namespace types;
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// select
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template <class A, class T, bool... Values, class = std::enable_if_t<std::is_integral<T>::value>>
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XSIMD_INLINE batch<T, A> select(batch_bool_constant<T, A, Values...> const&, batch<T, A> const& true_br, batch<T, A> const& false_br, requires_arch<avx2_128>) noexcept
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{
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constexpr int mask = batch_bool_constant<T, A, Values...>::mask();
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XSIMD_IF_CONSTEXPR(sizeof(T) == 4)
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{
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return _mm_blend_epi32(false_br, true_br, mask);
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}
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else
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{
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return select(batch_bool_constant<T, A, Values...>(), true_br, false_br, avx_128 {});
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}
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}
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// bitwise_lshift
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template <class A, class T, class = std::enable_if_t<std::is_integral<T>::value>>
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XSIMD_INLINE batch<T, A> bitwise_lshift(batch<T, A> const& self, batch<T, A> const& other, requires_arch<avx2_128>) noexcept
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{
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XSIMD_IF_CONSTEXPR(sizeof(T) == 4)
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{
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return _mm_sllv_epi32(self, other);
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}
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else XSIMD_IF_CONSTEXPR(sizeof(T) == 8)
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{
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return _mm_sllv_epi64(self, other);
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}
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else
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{
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return bitwise_lshift(self, other, avx {});
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}
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}
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// bitwise_rshift
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template <class A, class T, class = std::enable_if_t<std::is_integral<T>::value>>
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XSIMD_INLINE batch<T, A> bitwise_rshift(batch<T, A> const& self, batch<T, A> const& other, requires_arch<avx2_128>) noexcept
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{
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if (std::is_signed<T>::value)
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{
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XSIMD_IF_CONSTEXPR(sizeof(T) == 4)
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{
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return _mm_srav_epi32(self, other);
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}
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else
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{
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return bitwise_rshift(self, other, avx_128 {});
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}
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}
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else
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{
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XSIMD_IF_CONSTEXPR(sizeof(T) == 4)
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{
79+
return _mm_srlv_epi32(self, other);
80+
}
81+
else XSIMD_IF_CONSTEXPR(sizeof(T) == 8)
82+
{
83+
return _mm_srlv_epi64(self, other);
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}
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else
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{
87+
return bitwise_rshift(self, other, avx_128 {});
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}
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}
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}
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// load_masked
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template <class A, bool... Values, class Mode>
94+
XSIMD_INLINE batch<int32_t, A> load_masked(int32_t const* mem, batch_bool_constant<int32_t, A, Values...> mask, convert<int32_t>, Mode, requires_arch<avx2_128>) noexcept
95+
{
96+
return _mm_maskload_epi32(mem, mask.as_batch());
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}
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template <class A, bool... Values, class Mode>
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XSIMD_INLINE batch<uint32_t, A> load_masked(uint32_t const* mem, batch_bool_constant<uint32_t, A, Values...> mask, convert<uint32_t>, Mode, requires_arch<avx2_128>) noexcept
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{
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return _mm_maskload_epi32((int32_t*)mem, mask.as_batch());
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}
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template <class A, bool... Values, class Mode>
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XSIMD_INLINE batch<int64_t, A> load_masked(int64_t const* mem, batch_bool_constant<int64_t, A, Values...> mask, convert<double>, Mode, requires_arch<avx_128>) noexcept
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{
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return _mm_maskload_epi64(mem, mask.as_batch());
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}
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template <class A, bool... Values, class Mode>
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XSIMD_INLINE batch<uint64_t, A> load_masked(uint64_t const* mem, batch_bool_constant<uint64_t, A, Values...> mask, convert<double>, Mode, requires_arch<avx_128>) noexcept
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{
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return _mm_maskload_epi64((int64_t*)mem, mask.as_batch());
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}
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// store_masked
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template <class A, bool... Values, class Mode>
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XSIMD_INLINE void store_masked(int32_t* mem, batch<int32_t, A> const& src, batch_bool_constant<int32_t, A, Values...> mask, Mode, requires_arch<avx2_128>) noexcept
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{
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return _mm_maskstore_epi32(mem, mask.as_batch(), src);
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}
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template <class A, bool... Values, class Mode>
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XSIMD_INLINE void store_masked(uint32_t* mem, batch<uint32_t, A> const& src, batch_bool_constant<uint32_t, A, Values...> mask, Mode, requires_arch<avx2_128>) noexcept
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{
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return _mm_maskstore_epi32((int32_t*)mem, mask.as_batch(), src);
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}
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template <class A, bool... Values, class Mode>
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XSIMD_INLINE void store_masked(int64_t* mem, batch<int64_t, A> const& src, batch_bool_constant<int64_t, A, Values...> mask, Mode, requires_arch<avx_128>) noexcept
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{
128+
return _mm_maskstore_epi64(mem, mask.as_batch(), src);
129+
}
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template <class A, bool... Values, class Mode>
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XSIMD_INLINE void store_masked(uint64_t* mem, batch<uint64_t, A> const& src, batch_bool_constant<uint64_t, A, Values...> mask, Mode, requires_arch<avx_128>) noexcept
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{
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return _mm_maskstore_epi64((int64_t*)mem, mask.as_batch(), src);
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}
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// gather
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template <class T, class A, class U, detail::enable_sized_integral_t<T, 4> = 0, detail::enable_sized_integral_t<U, 4> = 0>
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XSIMD_INLINE batch<T, A> gather(batch<T, A> const&, T const* src, batch<U, A> const& index,
139+
kernel::requires_arch<avx2_128>) noexcept
140+
{
141+
return _mm_i32gather_epi32(reinterpret_cast<const int*>(src), index, sizeof(T));
142+
}
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144+
template <class T, class A, class U, detail::enable_sized_integral_t<T, 8> = 0, detail::enable_sized_integral_t<U, 8> = 0>
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XSIMD_INLINE batch<T, A> gather(batch<T, A> const&, T const* src, batch<U, A> const& index,
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kernel::requires_arch<avx2_128>) noexcept
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{
148+
return _mm_i64gather_epi64(reinterpret_cast<const long long int*>(src), index, sizeof(T));
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}
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template <class A, class U,
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detail::enable_sized_integral_t<U, 4> = 0>
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XSIMD_INLINE batch<float, A> gather(batch<float, A> const&, float const* src,
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batch<U, A> const& index,
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kernel::requires_arch<avx2_128>) noexcept
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{
157+
return _mm_i32gather_ps(src, index, sizeof(float));
158+
}
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template <class A, class U, detail::enable_sized_integral_t<U, 8> = 0>
161+
XSIMD_INLINE batch<double, A> gather(batch<double, A> const&, double const* src,
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batch<U, A> const& index,
163+
requires_arch<avx2_128>) noexcept
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{
165+
return _mm_i64gather_pd(src, index, sizeof(double));
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}
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}
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}
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#endif

‎include/xsimd/arch/xsimd_isa.hpp‎

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@@ -63,6 +63,7 @@
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#if XSIMD_WITH_AVX2
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#include "./xsimd_avx2.hpp"
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#include "./xsimd_avx2_128.hpp"
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#endif
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#if XSIMD_WITH_FMA3_AVX2

‎include/xsimd/config/xsimd_arch.hpp‎

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@@ -163,7 +163,7 @@ namespace xsimd
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using all_x86_architectures = arch_list<
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avx512vnni<avx512vbmi2>, avx512vbmi2, avx512vbmi, avx512ifma, avx512pf, avx512vnni<avx512bw>, avx512bw, avx512er, avx512dq, avx512cd, avx512f,
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avxvnni, fma3<avx2>, avx2, fma3<avx>, avx, avx_128, fma4, fma3<sse4_2>,
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avxvnni, fma3<avx2>, avx2, fma3<avx>, avx, avx2_128, avx_128, fma4, fma3<sse4_2>,
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sse4_2, sse4_1, /*sse4a,*/ ssse3, sse3, sse2>;
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169169
using all_sve_architectures = arch_list<detail::sve<512>, detail::sve<256>, detail::sve<128>>;

‎include/xsimd/types/xsimd_avx2_register.hpp‎

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@@ -28,6 +28,18 @@ namespace xsimd
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static constexpr char const* name() noexcept { return "avx2"; }
2929
};
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/**
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* @ingroup architectures
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*
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* AVX2 instructions extension for 128 bits registers
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*/
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struct avx2_128 : avx_128
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{
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static constexpr bool supported() noexcept { return XSIMD_WITH_AVX2; }
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static constexpr bool available() noexcept { return true; }
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static constexpr char const* name() noexcept { return "avx2/128"; }
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};
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3143
#if XSIMD_WITH_AVX2
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3345
#if !XSIMD_WITH_AVX
@@ -37,6 +49,7 @@ namespace xsimd
3749
namespace types
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{
3951
XSIMD_DECLARE_SIMD_REGISTER_ALIAS(avx2, avx);
52+
XSIMD_DECLARE_SIMD_REGISTER_ALIAS(avx2_128, avx_128);
4053
}
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#endif
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}

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