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AntoinePrvAntoinePrv
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Add more x86 cpu feature
1 parent b434834 commit 659baf7

1 file changed

Lines changed: 73 additions & 1 deletion

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‎include/xsimd/config/xsimd_cpu_features_x86.hpp‎

Lines changed: 73 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -397,10 +397,16 @@ namespace xsimd
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sse4_2 = 20,
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/* Population count instruction (POPCNT). */
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popcnt = 23,
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/* Advanced Encryption Standard instruction set. */
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aes_ni = 25,
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/* OS has enabled XSAVE/XRSTOR for extended processor state management. */
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osxsave = 27,
402404
/* Advanced Vector Extensions (256-bit SIMD). */
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avx = 28,
406+
/* Half to single floating point conversion. */
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f16c = 29,
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/* On-chip random number generator. */
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rdrnd = 30,
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};
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enum class edx
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{
@@ -449,6 +455,10 @@ namespace xsimd
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avx512f = 16,
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/* AVX-512 Doubleword and Quadword instructions. */
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avx512dq = 17,
458+
/* Low-level access to the entropy-generating hardware. */
459+
rdseed = 18,
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/* Intel arbitrary precision add carry. */
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adx = 19,
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/* AVX-512 Integer Fused Multiply-Add instructions. */
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avx512ifma = 21,
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/* AVX-512 Prefetch instructions. */
@@ -457,23 +467,49 @@ namespace xsimd
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avx512er = 27,
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/* AVX-512 Conflict Detection instructions. */
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avx512cd = 28,
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/* Sha-1 and Sha-256 extension. */
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sha = 29,
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/* AVX-512 Byte and Word instructions. */
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avx512bw = 30,
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/* AVX-512 Vector Length Extensions for xmm and ymm registers. */
475+
avx512vl = 31,
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};
463477
enum class ecx
464478
{
465479
/* AVX-512 Vector Bit Manipulation instructions. */
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avx512vbmi = 1,
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/* AVX-512 Vector Bit Manipulation instructions 2. */
468482
avx512vbmi2 = 6,
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/* Galois Field instructions. */
484+
gfni = 8,
485+
/* Vector Advanced Encryption Standard instructions. */
486+
vaes = 9,
487+
/* Carry-less multiplication quadword instruction. */
488+
vpclmulqdq = 10,
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/* AVX-512 Vector Neural Network instructions. */
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avx512vnni_bw = 11,
491+
/* AVX-512 bit algorithm instructions (BITALG). */
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avx512_bitalg = 12,
493+
/* AVX-512 vector population count for doubleword and quadword. */
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avx512_vpopcntdq = 14,
495+
};
496+
enum class edx {
497+
/* AVX-512 4-register neural network instructions (word variable precision). */
498+
avx512_4vnniw = 2,
499+
/* AVX-512 4-register multiply-accumulate single precision. */
500+
avx512_4fmaps = 3,
501+
/* AVX-512 intersect pairs of packed doubleword/quadword integers. */
502+
avx512_vp2intersect = 8,
503+
/* AVX-512 16-bit floating-point instructions. */
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avx512_fp16 = 23,
505+
471506
};
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473508
using regs_t = detail::x86_cpuid_regs<leaf, subleaf,
474509
detail::x86_reg_id<eax, 0>,
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detail::x86_reg_id<ebx, 1>,
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detail::x86_reg_id<ecx, 2>>;
511+
detail::x86_reg_id<ecx, 2>,
512+
detail::x86_reg_id<edx, 3>>;
477513
};
478514

479515
/**
@@ -497,6 +533,8 @@ namespace xsimd
497533
{
498534
/* AVX (VEX-encoded) Vector Neural Network instructions. */
499535
avxvnni = 4,
536+
/* AVX-512 BFloat16 instructions. */
537+
avx512_bf16 = 5,
500538
};
501539

502540
using regs_t = detail::x86_cpuid_regs<leaf, subleaf,
@@ -818,6 +856,12 @@ namespace xsimd
818856

819857
inline bool avx() const noexcept { return avx_enabled() && leaf1().all_bits_set<x86_cpuid_leaf1::ecx::avx>(); }
820858

859+
inline bool aes_ni() const noexcept { return sse_enabled() && leaf1().all_bits_set<x86_cpuid_leaf1::ecx::aes_ni>(); }
860+
861+
inline bool f16c() const noexcept { return avx_enabled() && leaf1().all_bits_set<x86_cpuid_leaf1::ecx::f16c>(); }
862+
863+
inline bool rdrnd() const noexcept { return leaf1().all_bits_set<x86_cpuid_leaf1::ecx::rdrnd>(); }
864+
821865
inline bool bmi1() const noexcept { return leaf7().all_bits_set<x86_cpuid_leaf7::ebx::bmi1>(); }
822866

823867
inline bool avx2() const noexcept { return avx_enabled() && leaf7().all_bits_set<x86_cpuid_leaf7::ebx::avx2>(); }
@@ -828,6 +872,10 @@ namespace xsimd
828872

829873
inline bool avx512dq() const noexcept { return avx512_enabled() && leaf7().all_bits_set<x86_cpuid_leaf7::ebx::avx512dq>(); }
830874

875+
inline bool rdseed() const noexcept { return leaf7().all_bits_set<x86_cpuid_leaf7::ebx::rdseed>(); }
876+
877+
inline bool adx() const noexcept { return leaf7().all_bits_set<x86_cpuid_leaf7::ebx::adx>(); }
878+
831879
inline bool avx512ifma() const noexcept { return avx512_enabled() && leaf7().all_bits_set<x86_cpuid_leaf7::ebx::avx512ifma>(); }
832880

833881
inline bool avx512pf() const noexcept { return avx512_enabled() && leaf7().all_bits_set<x86_cpuid_leaf7::ebx::avx512pf>(); }
@@ -836,16 +884,40 @@ namespace xsimd
836884

837885
inline bool avx512cd() const noexcept { return avx512_enabled() && leaf7().all_bits_set<x86_cpuid_leaf7::ebx::avx512cd>(); }
838886

887+
inline bool sha() const noexcept { return leaf7().all_bits_set<x86_cpuid_leaf7::ebx::sha>(); }
888+
839889
inline bool avx512bw() const noexcept { return avx512_enabled() && leaf7().all_bits_set<x86_cpuid_leaf7::ebx::avx512bw>(); }
840890

891+
inline bool avx512vl() const noexcept { return avx512_enabled() && leaf7().all_bits_set<x86_cpuid_leaf7::ebx::avx512vl>(); }
892+
841893
inline bool avx512vbmi() const noexcept { return avx512_enabled() && leaf7().all_bits_set<x86_cpuid_leaf7::ecx::avx512vbmi>(); }
842894

843895
inline bool avx512vbmi2() const noexcept { return avx512_enabled() && leaf7().all_bits_set<x86_cpuid_leaf7::ecx::avx512vbmi2>(); }
844896

897+
inline bool gfni() const noexcept { return avx512_enabled() && leaf7().all_bits_set<x86_cpuid_leaf7::ecx::gfni>(); }
898+
899+
inline bool vaes() const noexcept { return avx512_enabled() && leaf7().all_bits_set<x86_cpuid_leaf7::ecx::vaes>(); }
900+
901+
inline bool vpclmulqdq() const noexcept { return avx512_enabled() && leaf7().all_bits_set<x86_cpuid_leaf7::ecx::vpclmulqdq>(); }
902+
845903
inline bool avx512vnni_bw() const noexcept { return avx512_enabled() && leaf7().all_bits_set<x86_cpuid_leaf7::ecx::avx512vnni_bw>(); }
846904

905+
inline bool avx512_bitalg() const noexcept { return avx512_enabled() && leaf7().all_bits_set<x86_cpuid_leaf7::ecx::avx512_bitalg>(); }
906+
907+
inline bool avx512_vpopcntdq() const noexcept { return avx512_enabled() && leaf7().all_bits_set<x86_cpuid_leaf7::ecx::avx512_vpopcntdq>(); }
908+
909+
inline bool avx512_4vnniw() const noexcept { return avx512_enabled() && leaf7().all_bits_set<x86_cpuid_leaf7::edx::avx512_4vnniw>(); }
910+
911+
inline bool avx512_4fmaps() const noexcept { return avx512_enabled() && leaf7().all_bits_set<x86_cpuid_leaf7::edx::avx512_4fmaps>(); }
912+
913+
inline bool avx512_vp2intersect() const noexcept { return avx512_enabled() && leaf7().all_bits_set<x86_cpuid_leaf7::edx::avx512_vp2intersect>(); }
914+
915+
inline bool avx512_fp16() const noexcept { return avx512_enabled() && leaf7().all_bits_set<x86_cpuid_leaf7::edx::avx512_fp16>(); }
916+
847917
inline bool avxvnni() const noexcept { return avx_enabled() && leaf7sub1().all_bits_set<x86_cpuid_leaf7sub1::eax::avxvnni>(); }
848918

919+
inline bool avx512_bf16() const noexcept { return avx512_enabled() && leaf7sub1().all_bits_set<x86_cpuid_leaf7sub1::eax::avx512_bf16>(); }
920+
849921
inline bool fma4() const noexcept { return avx_enabled() && leaf80000001().all_bits_set<x86_cpuid_leaf80000001::ecx::fma4>(); }
850922
};
851923

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