1212#ifndef XSIMD_CPU_FEATURES_X86_HPP
1313#define XSIMD_CPU_FEATURES_X86_HPP
1414
15+ #include < array>
1516#include < cstdint>
1617
1718#include " ./config/xsimd_config.hpp"
@@ -25,9 +26,11 @@ namespace xsimd
2526{
2627 namespace detail
2728 {
28- inline void get_cpuid (int reg[4 ], int level, int count = 0 ) noexcept ;
29+ using cpuid_reg_t = std::array<int , 4 >;
30+ inline cpuid_reg_t get_cpuid (int level, int count = 0 ) noexcept ;
2931
30- inline std::uint32_t get_xcr0_low () noexcept ;
32+ using xcr0_reg_t = std::uint32_t ;
33+ inline xcr0_reg_t get_xcr0_low () noexcept ;
3134 }
3235
3336 /*
@@ -42,7 +45,7 @@ namespace xsimd
4245 class x86_xcr0
4346 {
4447 public:
45- using reg_t = std:: uint32_t ;
48+ using reg_t = detail:: xcr0_reg_t ;
4649
4750 /* * Parse a XCR0 value into individual components. */
4851 constexpr explicit x86_xcr0 (reg_t low) noexcept
@@ -81,15 +84,15 @@ namespace xsimd
8184 }
8285
8386 private:
84- std:: uint32_t m_low = {};
87+ reg_t m_low = {};
8588 };
8689
8790 class x86_cpu_id
8891 {
8992 public:
9093 struct cpu_id_regs
9194 {
92- using reg_t = int [ 4 ] ;
95+ using reg_t = detail:: cpuid_reg_t ;
9396
9497 reg_t reg1 = {};
9598 reg_t reg7 = {};
@@ -113,10 +116,10 @@ namespace xsimd
113116 inline static x86_cpu_id read ()
114117 {
115118 cpu_id_regs regs = {};
116- detail::get_cpuid (regs. reg1 , 0x1 );
117- detail::get_cpuid (regs. reg7 , 0x7 );
118- detail::get_cpuid (regs. reg7a , 0x7 , 0x1 );
119- detail::get_cpuid (regs. reg8 , 0x80000001 );
119+ regs. reg1 = detail::get_cpuid (0x1 );
120+ regs. reg7 = detail::get_cpuid (0x7 );
121+ regs. reg7a = detail::get_cpuid (0x7 , 0x1 );
122+ regs. reg8 = detail::get_cpuid (0x80000001 );
120123 return x86_cpu_id (regs);
121124 }
122125
@@ -241,15 +244,12 @@ namespace xsimd
241244
242245 namespace detail
243246 {
244- inline void get_cpuid (int reg[ 4 ], int level, int count) noexcept
247+ inline cpuid_reg_t get_cpuid (int level, int count) noexcept
245248 {
246249#if !XSIMD_TARGET_X86
247- reg[0 ] = 0 ;
248- reg[1 ] = 0 ;
249- reg[2 ] = 0 ;
250- reg[3 ] = 0 ;
251250 (void )level;
252251 (void )count;
252+ return {}; // All bits to zero
253253
254254#elif defined(_MSC_VER)
255255 __cpuidex (reg, level, count);
@@ -275,16 +275,16 @@ namespace xsimd
275275#endif
276276 }
277277
278- inline std:: uint32_t get_xcr0_low () noexcept
278+ inline xcr0_reg_t get_xcr0_low () noexcept
279279 {
280280#if !XSIMD_TARGET_X86
281- return {}; // return 0;
281+ return {}; // All bits to zero
282282
283283#elif defined(_MSC_VER) && _MSC_VER >= 1400
284- return static_cast <std:: uint32_t >(_xgetbv (0 ));
284+ return static_cast <xcr0_reg_t >(_xgetbv (0 ));
285285
286286#elif defined(__GNUC__)
287- std:: uint32_t xcr0 = {};
287+ xcr0_reg_t xcr0 = {};
288288 __asm__ (
289289 " xorl %%ecx, %%ecx\n "
290290 " xgetbv\n "
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