Improve x86 cpu feature code clarity

Author: AntoinePrv

include/xsimd/config/xsimd_cpu_features_x86.hpp

@@ -13,6 +13,7 @@
 #define XSIMD_CPU_FEATURES_X86_HPP
 
 #include <array>
+#include <cassert>
 #include <cstdint>
 
 #include "../utils/bits.hpp"
@@ -33,6 +34,104 @@ namespace xsimd
         inline xcr0_reg_t get_xcr0_low() noexcept;
     }
 
+    /**
+     * CPU Identification (CPUID) instruction results.
+     *
+     * The CPUID instruction provides detailed information about the processor,
+     * including supported instruction set extensions (SSE, AVX, AVX-512, etc.).
+     * This utility parses CPUID leaf values to detect available CPU features.
+     *
+     * @see https://en.wikipedia.org/wiki/CPUID
+     */
+    class x86_cpu_id
+    {
+    public:
+        /** Read the CpuId registers from the CPU if on the correct architecture. */
+        inline static x86_cpu_id read()
+        {
+            cpu_id_regs regs = {};
+            // TODO(C++20): Use designated initializer
+            regs.reg1 = detail::get_cpuid(0x1);
+            regs.reg7 = detail::get_cpuid(0x7);
+            regs.reg7a = detail::get_cpuid(0x7, 0x1);
+            regs.reg8 = detail::get_cpuid(0x80000001);
+            return x86_cpu_id(regs);
+        }
+
+        /** Create a value which return false to everything. */
+        constexpr x86_cpu_id() noexcept = default;
+
+        constexpr bool sse2() const noexcept { return utils::all_bits_set<26>(m_regs.reg1[3]); }
+
+        constexpr bool sse3() const noexcept { return utils::all_bits_set<0>(m_regs.reg1[2]); }
+
+        constexpr bool ssse3() const noexcept { return utils::all_bits_set<9>(m_regs.reg1[2]); }
+
+        constexpr bool sse4_1() const noexcept { return utils::all_bits_set<19>(m_regs.reg1[2]); }
+
+        constexpr bool sse4_2() const noexcept { return utils::all_bits_set<20>(m_regs.reg1[2]); }
+
+        constexpr bool fma3() const noexcept { return utils::all_bits_set<12>(m_regs.reg1[2]); }
+
+        /**
+         * Indicates whether the OS has enabled extended state management.
+         *
+         * When true, the OS has set bit 18 (OSXSAVE) in the CR4 control register,
+         * enabling the XGETBV/XSETBV instructions to access XCR0 and support
+         * processor extended state management using XSAVE/XRSTOR.
+         *
+         * This value is read from CPUID leaf 0x1, ECX bit 27, which reflects
+         * the state of CR4.OSXSAVE.
+         */
+        constexpr bool osxsave() const noexcept { return utils::all_bits_set<27>(m_regs.reg1[2]); }
+
+        constexpr bool avx() const noexcept { return utils::all_bits_set<28>(m_regs.reg1[2]); }
+
+        constexpr bool avx2() const noexcept { return utils::all_bits_set<5>(m_regs.reg7[1]); }
+
+        constexpr bool avx512f() const noexcept { return utils::all_bits_set<16>(m_regs.reg7[1]); }
+
+        constexpr bool avx512dq() const noexcept { return utils::all_bits_set<17>(m_regs.reg7[1]); }
+
+        constexpr bool avx512ifma() const noexcept { return utils::all_bits_set<21>(m_regs.reg7[1]); }
+
+        constexpr bool avx512pf() const noexcept { return utils::all_bits_set<26>(m_regs.reg7[1]); }
+
+        constexpr bool avx512er() const noexcept { return utils::all_bits_set<27>(m_regs.reg7[1]); }
+
+        constexpr bool avx512cd() const noexcept { return utils::all_bits_set<28>(m_regs.reg7[1]); }
+
+        constexpr bool avx512bw() const noexcept { return utils::all_bits_set<30>(m_regs.reg7[1]); }
+
+        constexpr bool avx512vbmi() const noexcept { return utils::all_bits_set<1>(m_regs.reg7[2]); }
+
+        constexpr bool avx512vbmi2() const noexcept { return utils::all_bits_set<6>(m_regs.reg7[2]); }
+
+        constexpr bool avx512vnni_bw() const noexcept { return utils::all_bits_set<11>(m_regs.reg7[2]); }
+
+        constexpr bool avxvnni() const noexcept { return utils::all_bits_set<4>(m_regs.reg7a[0]); }
+
+        constexpr bool fma4() const noexcept { return utils::all_bits_set<16>(m_regs.reg8[2]); }
+
+    private:
+        struct cpu_id_regs
+        {
+            using reg_t = detail::cpuid_reg_t;
+
+            reg_t reg1 = {};
+            reg_t reg7 = {};
+            reg_t reg7a = {};
+            reg_t reg8 = {};
+        };
+
+        /** Parse CpuInfo register values into individual components. */
+        constexpr explicit x86_cpu_id(const cpu_id_regs& regs) noexcept
+            : m_regs(regs)
+        {
+        }
+        cpu_id_regs m_regs = {};
+    };
+
     /*
      * Extended Control Register 0 (XCR0).
      *
@@ -56,13 +155,20 @@ namespace xsimd
         constexpr static x86_xcr0 safe_default() noexcept
         {
             reg_t low = {};
-            low = utils::set_bit<static_cast<reg_t>(bit::sse)>(low);
+            low = utils::make_bit_mask(static_cast<reg_t>(bit::sse));
             return x86_xcr0(low);
         }
 
-        /** Read the XCR0 register from the CPU if on the correct architecture. */
+        /**
+         * Read the XCR0 register from the CPU if on the correct architecture.
+         *
+         * This is only safe to call if bit 18 of CR4.OSXSAVE has been set.
+         *
+         * @see cpu_id::osxsave
+         */
         inline static x86_xcr0 read()
         {
+            assert(x86_cpu_id::read().osxsave());
             return x86_xcr0(detail::get_xcr0_low());
         }
 
@@ -71,20 +177,20 @@ namespace xsimd
 
         constexpr bool sse_enabled() const noexcept
         {
-            return bit_is_set<bit::sse>(m_low);
+            return all_bits_set<bit::sse>(m_low);
         }
 
         constexpr bool avx_enabled() const noexcept
         {
             // Check both SSE and AVX bits even though AVX must imply SSE
-            return bit_is_set<bit::sse, bit::avx>(m_low);
+            return all_bits_set<bit::sse, bit::avx>(m_low);
         }
 
         constexpr bool avx512_enabled() const noexcept
         {
             // Check all SSE, AVX, and AVX512 bits even though AVX512 must
             // imply AVX and SSE
-            return bit_is_set<bit::sse, bit::avx, bit::zmm_hi256>(m_low);
+            return all_bits_set<bit::sse, bit::avx, bit::zmm_hi256>(m_low);
         }
 
     private:
@@ -108,14 +214,16 @@ namespace xsimd
             zmm_hi256 = 6,
             /** AVX-512 enabled and XSAVE support for upper ZMM registers. */
             hi16_zmm = 7,
+            /** Saving/restoring Intel Processor Trace state via XSAVE enabled.*/
+            processor_trace = 8,
             /** XSAVE support for PKRU register. */
             pkru = 9,
         };
 
         template <bit... Bits>
-        static constexpr bool bit_is_set(reg_t value) noexcept
+        static constexpr bool all_bits_set(reg_t value) noexcept
         {
-            return utils::bit_is_set<static_cast<reg_t>(Bits)...>(value);
+            return utils::all_bits_set<static_cast<reg_t>(Bits)...>(value);
         }
 
         /** Parse a XCR0 value into individual components. */
@@ -126,122 +234,14 @@ namespace xsimd
         reg_t m_low = {};
     };
 
-    /**
-     * CPU Identification (CPUID) instruction results.
-     *
-     * The CPUID instruction provides detailed information about the processor,
-     * including supported instruction set extensions (SSE, AVX, AVX-512, etc.).
-     * This utility parses CPUID leaf values to detect available CPU features.
-     *
-     * @see https://en.wikipedia.org/wiki/CPUID
-     */
-    class x86_cpu_id
-    {
-    public:
-        /**
-         * Read the CpuId registers from the CPU if on the correct architecture.
-         *
-         * This is only safe to call if bit 18 of CR4.OSXSAVE has been set.
-         *
-         * @see cpu_id::osxsave
-         */
-        inline static x86_cpu_id read()
-        {
-            cpu_id_regs regs = {};
-            // TODO(C++20): Use designated initializer
-            regs.reg1 = detail::get_cpuid(0x1);
-            regs.reg7 = detail::get_cpuid(0x7);
-            regs.reg7a = detail::get_cpuid(0x7, 0x1);
-            regs.reg8 = detail::get_cpuid(0x80000001);
-            return x86_cpu_id(regs);
-        }
-
-        /** Create a value which return false to everything. */
-        constexpr x86_cpu_id() noexcept = default;
-
-        constexpr bool sse2() const noexcept { return utils::bit_is_set<26>(m_regs.reg1[3]); }
-
-        constexpr bool sse3() const noexcept { return utils::bit_is_set<0>(m_regs.reg1[2]); }
-
-        constexpr bool ssse3() const noexcept { return utils::bit_is_set<9>(m_regs.reg1[2]); }
-
-        constexpr bool sse4_1() const noexcept { return utils::bit_is_set<19>(m_regs.reg1[2]); }
-
-        constexpr bool sse4_2() const noexcept { return utils::bit_is_set<20>(m_regs.reg1[2]); }
-
-        constexpr bool fma3() const noexcept { return utils::bit_is_set<12>(m_regs.reg1[2]); }
-
-        /**
-         * Indicates whether the OS has enabled extended state management.
-         *
-         * When true, the OS has set bit 18 (OSXSAVE) in the CR4 control register,
-         * enabling the XGETBV/XSETBV instructions to access XCR0 and support
-         * processor extended state management using XSAVE/XRSTOR.
-         *
-         * This value is read from CPUID leaf 0x1, ECX bit 27, which reflects
-         * the state of CR4.OSXSAVE.
-         */
-        constexpr bool osxsave() const noexcept { return utils::bit_is_set<27>(m_regs.reg1[2]); }
-
-        constexpr bool avx() const noexcept { return utils::bit_is_set<28>(m_regs.reg1[2]); }
-
-        constexpr bool avx2() const noexcept { return utils::bit_is_set<5>(m_regs.reg7[1]); }
-
-        constexpr bool avx512f() const noexcept { return utils::bit_is_set<16>(m_regs.reg7[1]); }
-
-        constexpr bool avx512dq() const noexcept { return utils::bit_is_set<17>(m_regs.reg7[1]); }
-
-        constexpr bool avx512ifma() const noexcept { return utils::bit_is_set<21>(m_regs.reg7[1]); }
-
-        constexpr bool avx512pf() const noexcept { return utils::bit_is_set<26>(m_regs.reg7[1]); }
-
-        constexpr bool avx512er() const noexcept { return utils::bit_is_set<27>(m_regs.reg7[1]); }
-
-        constexpr bool avx512cd() const noexcept { return utils::bit_is_set<28>(m_regs.reg7[1]); }
-
-        constexpr bool avx512bw() const noexcept { return utils::bit_is_set<30>(m_regs.reg7[1]); }
-
-        constexpr bool avx512vbmi() const noexcept { return utils::bit_is_set<1>(m_regs.reg7[2]); }
-
-        constexpr bool avx512vbmi2() const noexcept { return utils::bit_is_set<6>(m_regs.reg7[2]); }
-
-        constexpr bool avx512vnni_bw() const noexcept { return utils::bit_is_set<11>(m_regs.reg7[2]); }
-
-        constexpr bool avxvnni() const noexcept { return utils::bit_is_set<4>(m_regs.reg7a[0]); }
-
-        constexpr bool fma4() const noexcept { return utils::bit_is_set<16>(m_regs.reg8[2]); }
-
-    private:
-        struct cpu_id_regs
-        {
-            using reg_t = detail::cpuid_reg_t;
-
-            reg_t reg1 = {};
-            reg_t reg7 = {};
-            reg_t reg7a = {};
-            reg_t reg8 = {};
-        };
-
-        /** Parse CpuInfo register values into individual components. */
-        constexpr explicit x86_cpu_id(const cpu_id_regs& regs) noexcept
-            : m_regs(regs)
-        {
-        }
-        cpu_id_regs m_regs = {};
-    };
-
     namespace detail
     {
+#if XSIMD_TARGET_X86
+
         inline cpuid_reg_t get_cpuid(int level, int count) noexcept
         {
             cpuid_reg_t reg = {};
-
-#if !XSIMD_TARGET_X86
-            (void)level;
-            (void)count;
-            return {}; // All bits to zero
-
-#elif defined(_MSC_VER)
+#if defined(_MSC_VER)
             __cpuidex(reg.data(), level, count);
 
 #elif defined(__INTEL_COMPILER)
@@ -268,11 +268,12 @@ namespace xsimd
 
         inline xcr0_reg_t get_xcr0_low() noexcept
         {
-#if !XSIMD_TARGET_X86
-            return {}; // All bits to zero
-
-#elif defined(_MSC_VER) && _MSC_VER >= 1400
+#if defined(_MSC_VER)
+#if _MSC_VER >= 1400
             return static_cast<xcr0_reg_t>(_xgetbv(0));
+#else
+#error "_MSC_VER < 1400 is not supported"
+#endif
 
 #elif defined(__GNUC__)
             xcr0_reg_t xcr0 = {};
@@ -288,11 +289,22 @@ namespace xsimd
 #endif
             );
             return xcr0;
+#endif
+        }
 
-#else /* _MSC_VER < 1400 */
-#error "_MSC_VER < 1400 is not supported"
-#endif /* _MSC_VER && _MSC_VER >= 1400 */
-        };
+#else // XSIMD_TARGET_X86
+
+        inline cpuid_reg_t get_cpuid(int level, int count) noexcept
+        {
+            return {}; // All bits to zero
+        }
+
+        inline xcr0_reg_t get_xcr0_low() noexcept
+        {
+            return {}; // All bits to zero
+        }
+
+#endif // XSIMD_TARGET_X86
     }
 }
 #endif

include/xsimd/config/xsimd_cpuid.hpp

@@ -115,7 +115,7 @@ namespace xsimd
                 rvv = bool(getauxval(AT_HWCAP) & HWCAP_V);
 #endif
 #endif
-                // Safe on all platforms, we simply be false
+                // Safe on all platforms, it will be all false if non x86.
                 const auto cpuid = xsimd::x86_cpu_id::read();
                 const auto xcr0 = cpuid.osxsave() ? x86_xcr0::read() : x86_xcr0::safe_default();
 

include/xsimd/utils/bits.hpp

@@ -12,13 +12,16 @@
 #ifndef XSIMD_CPUID_UTILS_HPP
 #define XSIMD_CPUID_UTILS_HPP
 
+#include <cassert>
 namespace xsimd
 {
     namespace utils
     {
         template <typename I>
         constexpr I make_bit_mask(I bit)
         {
+            assert(bit >= 0);
+            assert(bit < 8 * sizeof(I));
             return static_cast<I>(I { 1 } << bit);
         }
 
@@ -30,7 +33,7 @@ namespace xsimd
         }
 
         template <int... Bits, typename I>
-        constexpr bool bit_is_set(I value)
+        constexpr bool all_bits_set(I value)
         {
             constexpr I mask = make_bit_mask<I>(static_cast<I>(Bits)...);
             return (value & mask) == mask;