From 7b335b6c2f1d1f5019f7994e396afa59c3a376db Mon Sep 17 00:00:00 2001
From: serge-sans-paille <sergesanspaille@free.fr>
Date: Wed, 26 Nov 2025 08:35:10 +0100
Subject: [PATCH 1/2] [nits] Fix low-level lane size computation in AVX2

---
 include/xsimd/arch/xsimd_avx2.hpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/xsimd/arch/xsimd_avx2.hpp b/include/xsimd/arch/xsimd_avx2.hpp
index 2ee2a5241..f9628f450 100644
--- a/include/xsimd/arch/xsimd_avx2.hpp
+++ b/include/xsimd/arch/xsimd_avx2.hpp
@@ -193,7 +193,7 @@ namespace xsimd
         template <class A, class T, bool... Values, class Mode>
         XSIMD_INLINE void store_masked(T* mem, batch<T, A> const& src, batch_bool_constant<T, A, Values...> mask, Mode, requires_arch<avx2>) noexcept
         {
-            constexpr size_t lanes_per_half = sizeof(__m128i) / sizeof(T);
+            constexpr size_t lanes_per_half = batch<T, A>::size / 2;
 
             // confined to lower 128-bit half → forward to SSE
             XSIMD_IF_CONSTEXPR(mask.countl_zero() >= lanes_per_half)

From d67b318c016f16b0e8d4999cc879eb6d30989558 Mon Sep 17 00:00:00 2001
From: serge-sans-paille <sergesanspaille@free.fr>
Date: Wed, 26 Nov 2025 08:35:33 +0100
Subject: [PATCH 2/2] Add support for masked load in SVE

---
 include/xsimd/arch/xsimd_sve.hpp | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/include/xsimd/arch/xsimd_sve.hpp b/include/xsimd/arch/xsimd_sve.hpp
index 3fd08be1f..4d81311f0 100644
--- a/include/xsimd/arch/xsimd_sve.hpp
+++ b/include/xsimd/arch/xsimd_sve.hpp
@@ -39,6 +39,17 @@ namespace xsimd
             template <class T>
             svbool_t sve_ptrue() noexcept { return sve_ptrue_impl(index<sizeof(T)> {}); }
 
+            // predicate loading
+            template <bool M0, bool M1>
+            svbool_t sve_pmask() noexcept { return svdupq_b64(M0, M1); }
+            template <bool M0, bool M1, bool M2, bool M3>
+            svbool_t sve_pmask() noexcept { return svdupq_b32(M0, M1, M2, M3); }
+            template <bool M0, bool M1, bool M2, bool M3, bool M4, bool M5, bool M6, bool M7>
+            svbool_t sve_pmask() noexcept { return svdupq_b16(M0, M1, M2, M3, M4, M5, M6, M7); }
+            template <bool M0, bool M1, bool M2, bool M3, bool M4, bool M5, bool M6, bool M7,
+                      bool M8, bool M9, bool M10, bool M11, bool M12, bool M13, bool M14, bool M15>
+            svbool_t sve_pmask() noexcept { return svdupq_b8(M0, M1, M2, M3, M4, M5, M6, M7, M8, M9, M10, M11, M12, M13, M14, M15); }
+
             // count active lanes in a predicate
             XSIMD_INLINE uint64_t sve_pcount_impl(svbool_t p, index<1>) noexcept { return svcntp_b8(p, p); }
             XSIMD_INLINE uint64_t sve_pcount_impl(svbool_t p, index<2>) noexcept { return svcntp_b16(p, p); }
@@ -95,6 +106,13 @@ namespace xsimd
             return load_aligned<A>(src, convert<T>(), sve {});
         }
 
+        // load_masked
+        template <class A, class T, bool... Values, class Mode, detail::sve_enable_all_t<T> = 0>
+        XSIMD_INLINE batch<T, A> load_masked(T const* mem, batch_bool_constant<float, A, Values...> mask, Mode, requires_arch<sve>) noexcept
+        {
+            return svld1(detail::sve_pmask<Values...>(), reinterpret_cast<detail::sve_fix_char_t<T> const*>(mem));
+        }
+
         // load_complex
         template <class A, class T, detail::sve_enable_floating_point_t<T> = 0>
         XSIMD_INLINE batch<std::complex<T>, A> load_complex_aligned(std::complex<T> const* mem, convert<std::complex<T>>, requires_arch<sve>) noexcept