perf: collapse same-type aligned batch_bool_constant load to a select#1333
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DiamonDinoia wants to merge 1 commit intoxtensor-stack:masterfrom
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perf: collapse same-type aligned batch_bool_constant load to a select#1333DiamonDinoia wants to merge 1 commit intoxtensor-stack:masterfrom
DiamonDinoia wants to merge 1 commit intoxtensor-stack:masterfrom
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The cross-type ``load_masked`` overload for ``batch_bool_constant`` builds
the result via a per-lane scalar buffer:
for (i = 0; i < size; ++i)
buffer[i] = mask[i] ? T(mem[i]) : T(0);
GCC -O3 -DNDEBUG folds this for wide types (4-lane f32: 4 instructions
``movd + pinsrq``) but not for narrow types — for a 16-lane uint8_t mask
on SSE4.2 it emits ~50 asm lines of stack ``mov``/``shl``/``and``/``or``
round-trips through ``-0x18(%rsp)``.
Add a same-type, aligned-mode overload that lowers to ``select``
against the constant mask. Aligned mode guarantees the whole vector
lives in one alignment unit (alignof(A) >= sizeof(batch) on every
common-fallback arch), so an unconditional load cannot fault on
inactive lanes. The new overload is more specialized than the existing
``T_in, T_out, alignment`` template, so it wins overload resolution for
the same-type aligned case while leaving cross-type and unaligned paths
untouched.
Codegen probe (``g++ -O3 -DNDEBUG -msse4.2``):
function before after
load_aligned_const_u8 (mixed mask) ~50 inst 2 inst (``pand mem, k``)
load_aligned_const_f32 (T,F,T,F) 4 inst 2 inst (``pxor + blendps``)
Tests: 6 of 7 multi-arch builds (SSE2, SSE4.1, AVX2, AVX-512 via sde64,
RVV via qemu, emulated256) pass full ``test_xsimd``. AArch64 via qemu
shows 8 pre-existing test failures in ``[basic api] store_as(bool*,
batch_bool)`` reproduced on pristine master, unrelated to this change.
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The cross-type
load_maskedoverload forbatch_bool_constantbuilds the result via a per-lane scalar buffer:GCC -O3 -DNDEBUG folds this for wide types (4-lane f32: 4 instructions
movd + pinsrq) but not for narrow types — for a 16-lane uint8_t mask on SSE4.2 it emits ~50 asm lines of stackmov/shl/and/orround-trips through-0x18(%rsp).Add a same-type, aligned-mode overload that lowers to
selectagainst the constant mask. Aligned mode guarantees the whole vector lives in one alignment unit (alignof(A) >= sizeof(batch) on every common-fallback arch), so an unconditional load cannot fault on inactive lanes. The new overload is more specialized than the existingT_in, T_out, alignmenttemplate, so it wins overload resolution for the same-type aligned case while leaving cross-type and unaligned paths untouched.Codegen probe (
g++ -O3 -DNDEBUG -msse4.2):function before after
load_aligned_const_u8 (mixed mask) ~50 inst 2 inst (
pand mem, k)load_aligned_const_f32 (T,F,T,F) 4 inst 2 inst (
pxor + blendps)