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‎llvm/test/CodeGen/AArch64/bitreverse.ll‎

Lines changed: 148 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,6 @@
1-
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
22
; RUN: llc -mtriple=aarch64 %s -o - | FileCheck %s --check-prefixes=CHECK,SDAG
3+
; RUN: llc -mtriple=aarch64 -mattr=+sve %s -o - | FileCheck %s --check-prefixes=SVE
34
; RUN: llc -mtriple=aarch64 -global-isel -global-isel-abort=1 %s -o - | FileCheck %s --check-prefixes=CHECK,GISEL
45

56
; These tests just check that the plumbing is in place for @llvm.bitreverse.
@@ -14,6 +15,13 @@ define <2 x i16> @f(<2 x i16> %a) {
1415
; SDAG-NEXT: ushr v0.2s, v0.2s, #16
1516
; SDAG-NEXT: ret
1617
;
18+
; SVE-LABEL: f:
19+
; SVE: // %bb.0:
20+
; SVE-NEXT: rev32 v0.8b, v0.8b
21+
; SVE-NEXT: rbit v0.8b, v0.8b
22+
; SVE-NEXT: ushr v0.2s, v0.2s, #16
23+
; SVE-NEXT: ret
24+
;
1725
; GISEL-LABEL: f:
1826
; GISEL: // %bb.0:
1927
; GISEL-NEXT: uzp1 v0.4h, v0.4h, v0.4h
@@ -34,6 +42,12 @@ define i8 @g(i8 %a) {
3442
; CHECK-NEXT: rbit w8, w0
3543
; CHECK-NEXT: lsr w0, w8, #24
3644
; CHECK-NEXT: ret
45+
;
46+
; SVE-LABEL: g:
47+
; SVE: // %bb.0:
48+
; SVE-NEXT: rbit w8, w0
49+
; SVE-NEXT: lsr w0, w8, #24
50+
; SVE-NEXT: ret
3751
%b = call i8 @llvm.bitreverse.i8(i8 %a)
3852
ret i8 %b
3953
}
@@ -46,6 +60,12 @@ define i16 @g_16(i16 %a) {
4660
; CHECK-NEXT: rbit w8, w0
4761
; CHECK-NEXT: lsr w0, w8, #16
4862
; CHECK-NEXT: ret
63+
;
64+
; SVE-LABEL: g_16:
65+
; SVE: // %bb.0:
66+
; SVE-NEXT: rbit w8, w0
67+
; SVE-NEXT: lsr w0, w8, #16
68+
; SVE-NEXT: ret
4969
%b = call i16 @llvm.bitreverse.i16(i16 %a)
5070
ret i16 %b
5171
}
@@ -57,6 +77,11 @@ define i32 @g_32(i32 %a) {
5777
; CHECK: // %bb.0:
5878
; CHECK-NEXT: rbit w0, w0
5979
; CHECK-NEXT: ret
80+
;
81+
; SVE-LABEL: g_32:
82+
; SVE: // %bb.0:
83+
; SVE-NEXT: rbit w0, w0
84+
; SVE-NEXT: ret
6085
%b = call i32 @llvm.bitreverse.i32(i32 %a)
6186
ret i32 %b
6287
}
@@ -68,6 +93,11 @@ define i64 @g_64(i64 %a) {
6893
; CHECK: // %bb.0:
6994
; CHECK-NEXT: rbit x0, x0
7095
; CHECK-NEXT: ret
96+
;
97+
; SVE-LABEL: g_64:
98+
; SVE: // %bb.0:
99+
; SVE-NEXT: rbit x0, x0
100+
; SVE-NEXT: ret
71101
%b = call i64 @llvm.bitreverse.i64(i64 %a)
72102
ret i64 %b
73103
}
@@ -81,6 +111,13 @@ define i128 @g_128(i128 %a) {
81111
; CHECK-NEXT: rbit x1, x0
82112
; CHECK-NEXT: mov x0, x8
83113
; CHECK-NEXT: ret
114+
;
115+
; SVE-LABEL: g_128:
116+
; SVE: // %bb.0:
117+
; SVE-NEXT: rbit x8, x1
118+
; SVE-NEXT: rbit x1, x0
119+
; SVE-NEXT: mov x0, x8
120+
; SVE-NEXT: ret
84121
%b = call i128 @llvm.bitreverse.i128(i128 %a)
85122
ret i128 %b
86123
}
@@ -93,6 +130,12 @@ define <16 x i3> @g_vec_16x3(<16 x i3> %a) {
93130
; CHECK-NEXT: rbit v0.16b, v0.16b
94131
; CHECK-NEXT: ushr v0.16b, v0.16b, #5
95132
; CHECK-NEXT: ret
133+
;
134+
; SVE-LABEL: g_vec_16x3:
135+
; SVE: // %bb.0:
136+
; SVE-NEXT: rbit v0.16b, v0.16b
137+
; SVE-NEXT: ushr v0.16b, v0.16b, #5
138+
; SVE-NEXT: ret
96139
%b = call <16 x i3> @llvm.bitreverse.v16i3(<16 x i3> %a)
97140
ret <16 x i3> %b
98141
}
@@ -105,6 +148,12 @@ define <16 x i4> @g_vec_16x4(<16 x i4> %a) {
105148
; CHECK-NEXT: rbit v0.16b, v0.16b
106149
; CHECK-NEXT: ushr v0.16b, v0.16b, #4
107150
; CHECK-NEXT: ret
151+
;
152+
; SVE-LABEL: g_vec_16x4:
153+
; SVE: // %bb.0:
154+
; SVE-NEXT: rbit v0.16b, v0.16b
155+
; SVE-NEXT: ushr v0.16b, v0.16b, #4
156+
; SVE-NEXT: ret
108157
%b = call <16 x i4> @llvm.bitreverse.v16i4(<16 x i4> %a)
109158
ret <16 x i4> %b
110159
}
@@ -116,6 +165,11 @@ define <8 x i8> @g_vec(<8 x i8> %a) {
116165
; CHECK: // %bb.0:
117166
; CHECK-NEXT: rbit v0.8b, v0.8b
118167
; CHECK-NEXT: ret
168+
;
169+
; SVE-LABEL: g_vec:
170+
; SVE: // %bb.0:
171+
; SVE-NEXT: rbit v0.8b, v0.8b
172+
; SVE-NEXT: ret
119173
%b = call <8 x i8> @llvm.bitreverse.v8i8(<8 x i8> %a)
120174
ret <8 x i8> %b
121175
}
@@ -127,6 +181,11 @@ define <16 x i8> @g_vec_16x8(<16 x i8> %a) {
127181
; CHECK: // %bb.0:
128182
; CHECK-NEXT: rbit v0.16b, v0.16b
129183
; CHECK-NEXT: ret
184+
;
185+
; SVE-LABEL: g_vec_16x8:
186+
; SVE: // %bb.0:
187+
; SVE-NEXT: rbit v0.16b, v0.16b
188+
; SVE-NEXT: ret
130189
%b = call <16 x i8> @llvm.bitreverse.v16i8(<16 x i8> %a)
131190
ret <16 x i8> %b
132191
}
@@ -139,6 +198,12 @@ define <32 x i8> @g_vec_32x8(<32 x i8> %a) {
139198
; CHECK-NEXT: rbit v0.16b, v0.16b
140199
; CHECK-NEXT: rbit v1.16b, v1.16b
141200
; CHECK-NEXT: ret
201+
;
202+
; SVE-LABEL: g_vec_32x8:
203+
; SVE: // %bb.0:
204+
; SVE-NEXT: rbit v0.16b, v0.16b
205+
; SVE-NEXT: rbit v1.16b, v1.16b
206+
; SVE-NEXT: ret
142207
%b = call <32 x i8> @llvm.bitreverse.v32i8(<32 x i8> %a)
143208
ret <32 x i8> %b
144209
}
@@ -153,6 +218,13 @@ define <4 x i8> @g_vec_4x8(<4 x i8> %a) {
153218
; SDAG-NEXT: ushr v0.4h, v0.4h, #8
154219
; SDAG-NEXT: ret
155220
;
221+
; SVE-LABEL: g_vec_4x8:
222+
; SVE: // %bb.0:
223+
; SVE-NEXT: rev16 v0.8b, v0.8b
224+
; SVE-NEXT: rbit v0.8b, v0.8b
225+
; SVE-NEXT: ushr v0.4h, v0.4h, #8
226+
; SVE-NEXT: ret
227+
;
156228
; GISEL-LABEL: g_vec_4x8:
157229
; GISEL: // %bb.0:
158230
; GISEL-NEXT: uzp1 v0.8b, v0.8b, v0.8b
@@ -171,6 +243,11 @@ define <9 x i8> @g_vec_9x8(<9 x i8> %a) {
171243
; CHECK: // %bb.0:
172244
; CHECK-NEXT: rbit v0.16b, v0.16b
173245
; CHECK-NEXT: ret
246+
;
247+
; SVE-LABEL: g_vec_9x8:
248+
; SVE: // %bb.0:
249+
; SVE-NEXT: rbit v0.16b, v0.16b
250+
; SVE-NEXT: ret
174251
%b = call <9 x i8> @llvm.bitreverse.v9i8(<9 x i8> %a)
175252
ret <9 x i8> %b
176253
}
@@ -183,6 +260,12 @@ define <4 x i16> @g_vec_4x16(<4 x i16> %a) {
183260
; CHECK-NEXT: rev16 v0.8b, v0.8b
184261
; CHECK-NEXT: rbit v0.8b, v0.8b
185262
; CHECK-NEXT: ret
263+
;
264+
; SVE-LABEL: g_vec_4x16:
265+
; SVE: // %bb.0:
266+
; SVE-NEXT: rev16 v0.8b, v0.8b
267+
; SVE-NEXT: rbit v0.8b, v0.8b
268+
; SVE-NEXT: ret
186269
%b = call <4 x i16> @llvm.bitreverse.v4i16(<4 x i16> %a)
187270
ret <4 x i16> %b
188271
}
@@ -195,6 +278,12 @@ define <8 x i16> @g_vec_8x16(<8 x i16> %a) {
195278
; CHECK-NEXT: rev16 v0.16b, v0.16b
196279
; CHECK-NEXT: rbit v0.16b, v0.16b
197280
; CHECK-NEXT: ret
281+
;
282+
; SVE-LABEL: g_vec_8x16:
283+
; SVE: // %bb.0:
284+
; SVE-NEXT: rev16 v0.16b, v0.16b
285+
; SVE-NEXT: rbit v0.16b, v0.16b
286+
; SVE-NEXT: ret
198287
%b = call <8 x i16> @llvm.bitreverse.v8i16(<8 x i16> %a)
199288
ret <8 x i16> %b
200289
}
@@ -209,6 +298,14 @@ define <16 x i16> @g_vec_16x16(<16 x i16> %a) {
209298
; CHECK-NEXT: rbit v0.16b, v0.16b
210299
; CHECK-NEXT: rbit v1.16b, v1.16b
211300
; CHECK-NEXT: ret
301+
;
302+
; SVE-LABEL: g_vec_16x16:
303+
; SVE: // %bb.0:
304+
; SVE-NEXT: rev16 v0.16b, v0.16b
305+
; SVE-NEXT: rev16 v1.16b, v1.16b
306+
; SVE-NEXT: rbit v0.16b, v0.16b
307+
; SVE-NEXT: rbit v1.16b, v1.16b
308+
; SVE-NEXT: ret
212309
%b = call <16 x i16> @llvm.bitreverse.v16i16(<16 x i16> %a)
213310
ret <16 x i16> %b
214311
}
@@ -221,6 +318,12 @@ define <2 x i32> @g_vec_2x32(<2 x i32> %a) {
221318
; CHECK-NEXT: rev32 v0.8b, v0.8b
222319
; CHECK-NEXT: rbit v0.8b, v0.8b
223320
; CHECK-NEXT: ret
321+
;
322+
; SVE-LABEL: g_vec_2x32:
323+
; SVE: // %bb.0:
324+
; SVE-NEXT: rev32 v0.8b, v0.8b
325+
; SVE-NEXT: rbit v0.8b, v0.8b
326+
; SVE-NEXT: ret
224327
%b = call <2 x i32> @llvm.bitreverse.v2i32(<2 x i32> %a)
225328
ret <2 x i32> %b
226329
}
@@ -233,6 +336,12 @@ define <4 x i32> @g_vec_4x32(<4 x i32> %a) {
233336
; CHECK-NEXT: rev32 v0.16b, v0.16b
234337
; CHECK-NEXT: rbit v0.16b, v0.16b
235338
; CHECK-NEXT: ret
339+
;
340+
; SVE-LABEL: g_vec_4x32:
341+
; SVE: // %bb.0:
342+
; SVE-NEXT: rev32 v0.16b, v0.16b
343+
; SVE-NEXT: rbit v0.16b, v0.16b
344+
; SVE-NEXT: ret
236345
%b = call <4 x i32> @llvm.bitreverse.v4i32(<4 x i32> %a)
237346
ret <4 x i32> %b
238347
}
@@ -247,6 +356,14 @@ define <8 x i32> @g_vec_8x32(<8 x i32> %a) {
247356
; CHECK-NEXT: rbit v0.16b, v0.16b
248357
; CHECK-NEXT: rbit v1.16b, v1.16b
249358
; CHECK-NEXT: ret
359+
;
360+
; SVE-LABEL: g_vec_8x32:
361+
; SVE: // %bb.0:
362+
; SVE-NEXT: rev32 v0.16b, v0.16b
363+
; SVE-NEXT: rev32 v1.16b, v1.16b
364+
; SVE-NEXT: rbit v0.16b, v0.16b
365+
; SVE-NEXT: rbit v1.16b, v1.16b
366+
; SVE-NEXT: ret
250367
%b = call <8 x i32> @llvm.bitreverse.v8i32(<8 x i32> %a)
251368
ret <8 x i32> %b
252369
}
@@ -260,6 +377,12 @@ define <1 x i64> @g_vec_1x64(<1 x i64> %a) {
260377
; SDAG-NEXT: rbit v0.8b, v0.8b
261378
; SDAG-NEXT: ret
262379
;
380+
; SVE-LABEL: g_vec_1x64:
381+
; SVE: // %bb.0:
382+
; SVE-NEXT: rev64 v0.8b, v0.8b
383+
; SVE-NEXT: rbit v0.8b, v0.8b
384+
; SVE-NEXT: ret
385+
;
263386
; GISEL-LABEL: g_vec_1x64:
264387
; GISEL: // %bb.0:
265388
; GISEL-NEXT: fmov x8, d0
@@ -278,6 +401,12 @@ define <2 x i64> @g_vec_2x64(<2 x i64> %a) {
278401
; CHECK-NEXT: rev64 v0.16b, v0.16b
279402
; CHECK-NEXT: rbit v0.16b, v0.16b
280403
; CHECK-NEXT: ret
404+
;
405+
; SVE-LABEL: g_vec_2x64:
406+
; SVE: // %bb.0:
407+
; SVE-NEXT: rev64 v0.16b, v0.16b
408+
; SVE-NEXT: rbit v0.16b, v0.16b
409+
; SVE-NEXT: ret
281410
%b = call <2 x i64> @llvm.bitreverse.v2i64(<2 x i64> %a)
282411
ret <2 x i64> %b
283412
}
@@ -292,6 +421,14 @@ define <4 x i64> @g_vec_4x64(<4 x i64> %a) {
292421
; CHECK-NEXT: rbit v0.16b, v0.16b
293422
; CHECK-NEXT: rbit v1.16b, v1.16b
294423
; CHECK-NEXT: ret
424+
;
425+
; SVE-LABEL: g_vec_4x64:
426+
; SVE: // %bb.0:
427+
; SVE-NEXT: rev64 v0.16b, v0.16b
428+
; SVE-NEXT: rev64 v1.16b, v1.16b
429+
; SVE-NEXT: rbit v0.16b, v0.16b
430+
; SVE-NEXT: rbit v1.16b, v1.16b
431+
; SVE-NEXT: ret
295432
%b = call <4 x i64> @llvm.bitreverse.v4i64(<4 x i64> %a)
296433
ret <4 x i64> %b
297434
}
@@ -308,6 +445,16 @@ define <2 x i128> @g_vec_2x128(<2 x i128> %a) {
308445
; CHECK-NEXT: mov x0, x8
309446
; CHECK-NEXT: mov x2, x9
310447
; CHECK-NEXT: ret
448+
;
449+
; SVE-LABEL: g_vec_2x128:
450+
; SVE: // %bb.0:
451+
; SVE-NEXT: rbit x8, x1
452+
; SVE-NEXT: rbit x9, x3
453+
; SVE-NEXT: rbit x1, x0
454+
; SVE-NEXT: rbit x3, x2
455+
; SVE-NEXT: mov x0, x8
456+
; SVE-NEXT: mov x2, x9
457+
; SVE-NEXT: ret
311458
%b = call <2 x i128> @llvm.bitreverse.v2i128(<2 x i128> %a)
312459
ret <2 x i128> %b
313460
}

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