@@ -1671,43 +1671,64 @@ impl Traces {
16711671 use super :: register:: cols:: NUM_COLUMNS as REGISTER_COLS ;
16721672 use super :: shift:: cols:: NUM_COLUMNS as SHIFT_COLS ;
16731673
1674+ let Traces {
1675+ cpus,
1676+ bitwise,
1677+ lts,
1678+ shifts,
1679+ memws,
1680+ memw_aligneds,
1681+ loads,
1682+ decode,
1683+ muls,
1684+ dvrms,
1685+ pages,
1686+ register,
1687+ branches,
1688+ halt,
1689+ commit,
1690+ memw_registers,
1691+ page_configs : _,
1692+ public_output_bytes : _,
1693+ } = self ;
1694+
16741695 let mut total: u64 = 0 ;
1675- for t in & self . cpus {
1696+ for t in cpus {
16761697 total += ( t. num_rows ( ) * CPU_COLS ) as u64 ;
16771698 }
1678- total += ( self . bitwise . num_rows ( ) * ( BITWISE_COLS - BITWISE_PRECOMPUTED ) ) as u64 ;
1679- for t in & self . lts {
1699+ total += ( bitwise. num_rows ( ) * ( BITWISE_COLS - BITWISE_PRECOMPUTED ) ) as u64 ;
1700+ for t in lts {
16801701 total += ( t. num_rows ( ) * LT_COLS ) as u64 ;
16811702 }
1682- for t in & self . shifts {
1703+ for t in shifts {
16831704 total += ( t. num_rows ( ) * SHIFT_COLS ) as u64 ;
16841705 }
1685- for t in & self . memws {
1706+ for t in memws {
16861707 total += ( t. num_rows ( ) * MEMW_COLS ) as u64 ;
16871708 }
1688- for t in & self . memw_aligneds {
1709+ for t in memw_aligneds {
16891710 total += ( t. num_rows ( ) * MEMW_A_COLS ) as u64 ;
16901711 }
1691- for t in & self . loads {
1712+ for t in loads {
16921713 total += ( t. num_rows ( ) * LOAD_COLS ) as u64 ;
16931714 }
1694- total += ( self . decode . num_rows ( ) * ( DECODE_COLS - DECODE_PRECOMPUTED ) ) as u64 ;
1695- for t in & self . muls {
1715+ total += ( decode. num_rows ( ) * ( DECODE_COLS - DECODE_PRECOMPUTED ) ) as u64 ;
1716+ for t in muls {
16961717 total += ( t. num_rows ( ) * MUL_COLS ) as u64 ;
16971718 }
1698- for t in & self . dvrms {
1719+ for t in dvrms {
16991720 total += ( t. num_rows ( ) * DVRM_COLS ) as u64 ;
17001721 }
1701- for t in & self . branches {
1722+ for t in branches {
17021723 total += ( t. num_rows ( ) * BRANCH_COLS ) as u64 ;
17031724 }
1704- total += ( self . halt . num_rows ( ) * HALT_COLS ) as u64 ;
1705- total += ( self . commit . num_rows ( ) * COMMIT_COLS ) as u64 ;
1706- total += ( self . register . num_rows ( ) * ( REGISTER_COLS - REGISTER_PREPROCESSED ) ) as u64 ;
1707- for t in & self . pages {
1725+ total += ( halt. num_rows ( ) * HALT_COLS ) as u64 ;
1726+ total += ( commit. num_rows ( ) * COMMIT_COLS ) as u64 ;
1727+ total += ( register. num_rows ( ) * ( REGISTER_COLS - REGISTER_PREPROCESSED ) ) as u64 ;
1728+ for t in pages {
17081729 total += ( t. num_rows ( ) * ( PAGE_COLS - PAGE_PREPROCESSED ) ) as u64 ;
17091730 }
1710- for t in & self . memw_registers {
1731+ for t in memw_registers {
17111732 total += ( t. num_rows ( ) * MEMW_R_COLS ) as u64 ;
17121733 }
17131734 total
@@ -1743,43 +1764,64 @@ impl Traces {
17431764 let n_page = aux_cols ( super :: page:: bus_interactions ( 0 ) . len ( ) ) ;
17441765 let n_memw_r = aux_cols ( super :: memw_register:: bus_interactions ( ) . len ( ) ) ;
17451766
1767+ let Traces {
1768+ cpus,
1769+ bitwise,
1770+ lts,
1771+ shifts,
1772+ memws,
1773+ memw_aligneds,
1774+ loads,
1775+ decode,
1776+ muls,
1777+ dvrms,
1778+ pages,
1779+ register,
1780+ branches,
1781+ halt,
1782+ commit,
1783+ memw_registers,
1784+ page_configs : _,
1785+ public_output_bytes : _,
1786+ } = self ;
1787+
17461788 let mut total: u64 = 0 ;
1747- for t in & self . cpus {
1789+ for t in cpus {
17481790 total += ( t. num_rows ( ) * n_cpu) as u64 ;
17491791 }
1750- total += ( self . bitwise . num_rows ( ) * n_bitwise) as u64 ;
1751- for t in & self . lts {
1792+ total += ( bitwise. num_rows ( ) * n_bitwise) as u64 ;
1793+ for t in lts {
17521794 total += ( t. num_rows ( ) * n_lt) as u64 ;
17531795 }
1754- for t in & self . shifts {
1796+ for t in shifts {
17551797 total += ( t. num_rows ( ) * n_shift) as u64 ;
17561798 }
1757- for t in & self . memws {
1799+ for t in memws {
17581800 total += ( t. num_rows ( ) * n_memw) as u64 ;
17591801 }
1760- for t in & self . memw_aligneds {
1802+ for t in memw_aligneds {
17611803 total += ( t. num_rows ( ) * n_memw_a) as u64 ;
17621804 }
1763- for t in & self . loads {
1805+ for t in loads {
17641806 total += ( t. num_rows ( ) * n_load) as u64 ;
17651807 }
1766- total += ( self . decode . num_rows ( ) * n_decode) as u64 ;
1767- for t in & self . muls {
1808+ total += ( decode. num_rows ( ) * n_decode) as u64 ;
1809+ for t in muls {
17681810 total += ( t. num_rows ( ) * n_mul) as u64 ;
17691811 }
1770- for t in & self . dvrms {
1812+ for t in dvrms {
17711813 total += ( t. num_rows ( ) * n_dvrm) as u64 ;
17721814 }
1773- for t in & self . branches {
1815+ for t in branches {
17741816 total += ( t. num_rows ( ) * n_branch) as u64 ;
17751817 }
1776- total += ( self . halt . num_rows ( ) * n_halt) as u64 ;
1777- total += ( self . commit . num_rows ( ) * n_commit) as u64 ;
1778- total += ( self . register . num_rows ( ) * n_register) as u64 ;
1779- for t in & self . pages {
1818+ total += ( halt. num_rows ( ) * n_halt) as u64 ;
1819+ total += ( commit. num_rows ( ) * n_commit) as u64 ;
1820+ total += ( register. num_rows ( ) * n_register) as u64 ;
1821+ for t in pages {
17801822 total += ( t. num_rows ( ) * n_page) as u64 ;
17811823 }
1782- for t in & self . memw_registers {
1824+ for t in memw_registers {
17831825 total += ( t. num_rows ( ) * n_memw_r) as u64 ;
17841826 }
17851827 total
0 commit comments